SMSC LAN91C111 Datasheet
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SMSC LAN91C111 Datasheet

10/100 non-pci ethernet single chip mac + phy
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PRODUCT FEATURES

Single Chip Ethernet Controller
Dual Speed - 10/100 Mbps
Fully Supports Full Duplex Switched Ethernet
Supports Burst Data Transfer
8 Kbytes Internal Memory for Receive and Transmit
FIFO Buffers
Enhanced Power Management Features
Optional Configuration via Serial EEPROM Interface
Supports 8, 16 and 32 Bit CPU Accesses
Internal 32 Bit Wide Data Path (Into Packet Buffer
Memory)
Built-in Transparent Arbitration for Slave Sequential
Access Architecture
Flat MMU Architecture with Symmetric Transmit and
Receive Structures and Queues
3.3V Operation with 5V Tolerant IO Buffers (See Pin
List Description for Additional Details)
Single 25 MHz Reference Clock for Both PHY and
MAC
External 25Mhz-output pin for an external PHY
supporting PHYs physical media.
Low Power CMOS Design
Supports Multiple Embedded Processor Host
Interfaces
— ARM
— SH
— Power PC
— Coldfire
— 680X0, 683XX
— MIPS R3000
SMSC LAN91C111 REV C
LAN91C111
10/100 Non-PCI
Ethernet Single Chip
MAC + PHY
3.3V MII (Media Independent Interface) MAC-PHY
Interface Running at Nibble Rate
MII Management Serial Interface
128-Pin QFP package; lead-free RoHS compliant
package also available.
128-Pin TQFP package, 1.0 mm height; lead-free
RoHS compliant package also available.
Commercial Temperature Range from 0°C to 70°C
(LAN91C111)
Industrial Temperature Range from -40°C to 85°C
(LAN91C111i)
Network Interface
Fully Integrated IEEE 802.3/802.3u-100Base-TX/
10Base-T Physical Layer
Auto Negotiation: 10/100, Full / Half Duplex
On Chip Wave Shaping - No External Filters
Required
Adaptive Equalizer
Baseline Wander Correction
LED Outputs (User selectable – Up to 2 LED
functions at one time)
— Link
— Activity
— Full Duplex
— 10/100
— Transmit
— Receive
DATASHEET
Datasheet
Revision 1.91 (08-18-08)

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Summary of Contents for SMSC LAN91C111

  • Page 1: Product Features

    Interfaces — ARM — SH — Power PC — Coldfire — 680X0, 683XX — MIPS R3000 SMSC LAN91C111 REV C LAN91C111 10/100 Non-PCI Ethernet Single Chip MAC + PHY 3.3V MII (Media Independent Interface) MAC-PHY Interface Running at Nibble Rate MII Management Serial Interface 128-Pin QFP package;...
  • Page 2 Any and all such uses without prior written approval of an Officer of SMSC and further testing and/or modification will be fully at the risk of the customer. Copies of this document or other SMSC literature, as well as the Terms of Sale Agreement, may be obtained by visiting SMSC’s website at http://www.smsc.com.

  • Page 3: Table Of Contents

    I/O Space ..............45 SMSC LAN91C111 REV C DATASHEET Revision 1.91 (08-18-08)
  • Page 4 Chapter 14 Timing Diagrams ..........110 Revision 1.91 (08-18-08) 10/100 Non-PCI Ethernet Single Chip MAC + PHY DATASHEET Datasheet SMSC LAN91C111 REV C...
  • Page 5 Chapter 16 Revision History ..........128 SMSC LAN91C111 REV C Revision 1.91 (08-18-08)
  • Page 6 List of Figures Figure 2.1 Pin Configuration - LAN91C111-FEAST 128 PIN TQFP ......9 Figure 2.2 Pin Configuration - LAN91C111-FEAST 128 PIN QFP .
  • Page 7 List of Tables Table 4.1 LAN91C111 Pin Requirements (128 Pin QFP and 1.0mm TQFP package) ....14 Table 7.1 4B/5B Symbol Mapping ............27 Table 7.2 Transmit Level Adjust .

  • Page 8: Chapter 1 General Description

    (MI). Internal output wave shaping circuitry and on-chip filters eliminate the need for external filters normally required in 100Base-TX and 10Base-T applications. The LAN91C111 can automatically configure itself for 100 or 10 Mbps and Full or Half Duplex operation with the on-chip Auto-Negotiation algorithm. The LAN91C111 is ideal for media interfaces for embedded application desiring Ethernet connectivity as well as 100Base-TX/10Base-T adapter cards, motherboards, repeaters, switching hubs.

  • Page 9: Chapter 2 Pin Configurations

    TPO+ TPO- AVDD TPI+ TPI- AGND nLNK nLEDA nLEDB MCLK nCNTRL INTR0 RESET Figure 2.1 Pin Configuration - LAN91C111-FEAST 128 PIN TQFP SMSC LAN91C111 REV C Pin Configuration LAN91C111- FEAST 128 PIN TQFP DATASHEET nBE2 nBE1 nBE0 Revision 1.91 (08-18-08)

  • Page 10: Figure 2.2 Pin Configuration - Lan91C111-Feast 128 Pin Qfp

    MCLK nCNTRL INTR0 RESET nDATACS nCYCLE W/nR Figure 2.2 Pin Configuration - LAN91C111-FEAST 128 PIN QFP Revision 1.91 (08-18-08) 10/100 Non-PCI Ethernet Single Chip MAC + PHY Pin Configuration LAN91C111- FEAST 128 PIN QFP DATASHEET Datasheet nBE3...

  • Page 11: Chapter 3 Block Diagrams

    The diagram shown in Figure 3.1, "Basic Functional Block Diagram", describes the device basic functional blocks. The SMSC LAN91C111 is a single chip solution for embedded designs with minimal Host and external supporting devices required to implement 10/100 Ethernet connectivity solutions.

  • Page 12: Figure 3.2 Block Diagram

    Generic Embedded. The Host interface is an 8, 16 or 32 bit wide address / data bus with extensions for 32, 16 and 8 bit embedded RISC and ARM processors. The figure shown next page describes the SMSC LAN91C111 functional blocks required to integrate a 10/100 Ethernet Physical layer framer to the internal MAC.

  • Page 13: Figure 3.3 Lan91C111 Physical Layer To Internal Mac Block Diagram

    CRS100 COL100 RXD[3:0] RX_ER RX_DV RX25 SERIAL MCLK Manage -ment Power AUTONEG CONTROLS LOGIC Reset Figure 3.3 LAN91C111 Physical Layer to Internal MAC Block Diagram SMSC LAN91C111 REV C nPLED[0-5] LS[2-0]A Control LS[2-0]B DATASHEET Multiplexer LEDA Multiplexer Revision 1.91 (08-18-08)

  • Page 14: Chapter 4 Signal Descriptions

    Chapter 4 Signal Descriptions Table 4.1 LAN91C111 Pin Requirements (128 Pin QFP and 1.0mm TQFP package) FUNCTION System Address Bus System Data Bus System Control Bus Serial EEPROM LEDs Crystal Oscillator Power Ground Physical Interface (MII) MISC TOTAL Revision 1.91 (08-18-08)

  • Page 15: Chapter 5 Description Of Pin Functions

    DESCRIPTION TYPE A4-A15 Input. Decoded by LAN91C111 to determine access to its registers. A1-A3 Input. Used by LAN91C111 for internal register selection. Input. Used as an address qualifier. Address decoding is only enabled when AEN is low. nBE0- Input. Used during LAN91C111 register...
  • Page 16 Path can be accessed regardless of the values of AEN, A1-A15 and the content of the BANK SELECT Register. nDATACS provides an interface for bursting to and from the LAN91C111 32 bits at a time. DATASHEET Datasheet SMSC LAN91C111 REV C...
  • Page 17 EEPROM configurations. ENEEP I with Input. Enables (when high or open) pullup** LAN91C111 accesses to the serial EEPROM. Must be grounded if no EEPROM is connected to the LAN91C111. XTAL1 Iclk** An external 25 MHz crystal is connected XTAL2 across these pins.
  • Page 18 RX_ER I with Input. Indicates a code error detected by pulldown PHY. Used by the LAN91C111 to discard the packet being received. The error indication reported for this event is the same as a bad CRC (Receive Status Word bit 13).

  • Page 19: Chapter 6 Signal Description Parameters

    Datasheet Chapter 6 Signal Description Parameters This section provides a detailed description of each SMSC LAN91C111 signal. The signals are arranged in functional groups according to their associated function. The ‘n’ symbol at the beginning of a signal name indicates that it is an active low signal. When ‘n’ is not present before the signal name, it indicates an active high signal.

  • Page 20: Chapter 7 Functional Description

    It also determines the value of the transmit and receive interrupts as a function of the queues. The page size is 2048 bytes, with a maximum memory size of 8kbytes. MIR values are interpreted in 2048 byte units. Revision 1.91 (08-18-08) 10/100 Non-PCI Ethernet Single Chip MAC + PHY DATASHEET Datasheet SMSC LAN91C111 REV C...

  • Page 21: Biu Block

    The data path connection between the MAC and the internal PHY is provided by the internal MII. The LAN91C111 also supports the EXT_PHY mode for the use of an external PHY, such as HPNA. This mode isolates the internal PHY to allow interface with an external PHY through the MII pins.

  • Page 22: Management Data Timing

    7.1. The Ml serial port is idle when at Table 9.1 Figure 7.1 are start bits and need to be written as a 01 for the serial port DATASHEET Datasheet and timing diagram of a frame is SMSC LAN91C111 REV C...

  • Page 23: Figure 7.1 Mi Serial Port Frame Timing Diagram

    10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Figure 7.1 MI Serial Port Frame Timing Diagram SMSC LAN91C111 REV C Revision 1.91 (08-18-08) DATASHEET...

  • Page 24: Mii Packet Data Communication With External Phy

    7.5.4 MII Packet Data Communication with External PHY The MIl is a nibble wide packet data interface defined in IEEE 802.3. The LAN91C111 meets all the MIl requirements outlined in IEEE 802.3 and shown in TX_EN = 0 IDLE PREAMBLE...

  • Page 25: Serial Eeprom Interface

    RX_ER might be asserted during packet reception to signal the LAN91C111 that the present receive packet is invalid. The LAN91C111 will discard the packet by treating it as a CRC error. RXD0-RXD3 should always be aligned to packet nibbles, therefore, opening flag detection does not consider misaligned cases.

  • Page 26: Figure 7.3 Tx/10Bt Frame Format

    = [ 1 1] = [ DATA] Figure 7.3 TX/10BT Frame Format DATASHEET Datasheet INTERFRAME LLC DATA FCS LLC DATA IDLE BEFORE / AFTER 4B5B ENCODING, SCRAMBLING, AND MLT3 CODING LLC DATA FCS IDLE BEFORE / AFTER MANCHESTER ENCODING SMSC LAN91C111 REV C...

  • Page 27: Mii Disable

    The mapping of the 5B nibbles to the 4B code words is specified in IEEE 802.3. The 4B5B decoder on the LAN91C111 takes the 5B code words from the descrambler, converts them into 4B nibbles per Table 2, and sends the 4B nibbles to the controller interface. The 4B5B decoder also strips off the SSD delimiter (a.k.a.
  • Page 28 In Manchester coded data, the first half of the data bit contains the complement of the data, and the second half of the data bit contains the true data. The Manchester decoder in the LAN91C111 converts the Manchester encoded data stream from the TP receiver into NRZ data for the controller interface by decoding the data and stripping off the SOI pulse.

  • Page 29: Clock And Data Recovery

    100 Mbps 100BASE-TX requires scrambling to reduce the radiated emissions on the twisted pair. The LAN91C111 scrambler takes the encoded data from the 4B5B encoder, scrambles it per the IEEE 802.3 specifications, and sends it to the TP transmitter. 10 Mbps A scrambler is not used in 10Mbps mode.

  • Page 30: Twisted Pair Transmitter

    3/4/5 100 Ohm unshielded twisted pair cable or 150 Ohm shielded twisted pair cable tied directly to the TP output pins without any external filters. During the idle period, no output signal is transmitted on the TP outputs (except link pulse). Revision 1.91 (08-18-08) SMSC LAN91C111 REV C DATASHEET...

  • Page 31: Figure 7.4 Tp Output Voltage Template - 10 Mbps

    10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet -0.2 -0.4 -0.6 -0.8 -1.0 Figure 7.4 TP Output Voltage Template - 10 MBPS REFERENCE SMSC LAN91C111 REV C TIME (ns) TIME (NS) INTERNAL MAU DATASHEET 1 1 0 VOLTAGE (V) 0.55 0.45 -1.0 -0.55...

  • Page 32: Table 7.2 Transmit Level Adjust

    TIME (NS) INTERNAL MAU Table 7.2 Transmit Level Adjust DATASHEET Datasheet VOLTAGE (V) 0.15 -0.15 -1.0 -0.3 -0.7 -0.7 GAIN 1.16 1.14 1.12 1.10 1.08 1.06 1.04 1.02 1.00 0.98 0.96 0.94 0.92 0.90 0.88 0.86 SMSC LAN91C111 REV C...

  • Page 33: Twisted Pair Receiver

    The TP transmitter can be powered down by setting the transmit powerdown bit in the PHY Ml serial port Configuration 1 register. When the transmit powerdown bit is set, the TP transmitter is powered down, the TP transmit outputs are high impedance, and the rest of the LAN91C111 operates normally. 7.7.8...

  • Page 34: Figure 7.5 Tp Input Voltage Template -10Mbps

    10/100 Non-PCI Ethernet Single Chip MAC + PHY a. Short Bit 3.1V Slope 0.5 V/ ns 585mV 585 mV sin ( t/PW) b. Long Bit Slope 0.5 V/ ns t/PW) 585 mV sin [2 (t - PW/2)/PW] 3PW/4 PW/4 DATASHEET Datasheet 3.1V 585mV SMSC LAN91C111 REV C...

  • Page 35: Collision

    /I/I/ nor /J/K/ symbols but contains at least 2 non contiguous 0's, then activity is detected but the start of packet is considered to be faulty and a False Carrier Indication (also referred to as bad SMSC LAN91C111 REV C DATASHEET...

  • Page 36: End Of Packet

    The receive SOI pulse is detected by the TP receiver by sensing missing data transitions. Once the SOI pulse is detected, data reception is ended and the MAC is notified of no data/invalid data received. Revision 1.91 (08-18-08) SMSC LAN91C111 REV C DATASHEET...

  • Page 37: Link Integrity & Autonegotiation

    AutoNegotiation is only specified for 100BASE-TX and 10BASE-T operation. 10BASE-T Link Integrity Algorithm - 10Mbps The LAN91C111 uses the same 10BASE-T link integrity algorithm that is defined in IEEE 802.3 Clause 14. This algorithm uses normal link pulses, referred to as NLP's and transmitted during idle periods, to determine if a device has successfully established a link with a remote device (called Link Pass State).

  • Page 38: Figure 7.7 Link Pulse Output Voltage Template - Nlp, Flp

    IEEE 802.3 Clause 28. AutoNegotiation uses a burst of link pulses, called fast link pulses and referred to as FLP'S, to pass up to 16 bits of signaling data back and forth between the LAN91C111 and a remote device. The transmit FLP pulses meet the templated specified in IEEE 802.3 and shown Figure 7.7.

  • Page 39: Figure 7.8 Nlp Vs. Flp Link Pulse

    AutoNegotiation capable and is just transmitting either a 10BASE-T or 100BASE-TX signal, the LAN91C111 will sense that and place itself in the correct mode. If the LAN91C111 detects FLP's from the remote device, then the remote device is determined to have AutoNegotiation capability and the device then uses the contents of the Ml serial port AutoNegotiation Advertisement register and FLP's to advertise its capabilities to a remote device.

  • Page 40: Jabber

    PHY Ml serial port Status Output register. The LAN91C111 will automatically correct for the reverse polarity condition provided that the autopolarity feature is not disabled. Note: The first 3 received packets must be discarded after the correction of a reverse polarity condition.

  • Page 41: Full Duplex Mode

    7.7.17 PHY Powerdown The internal PHY of LAN91C111 can be powered down by setting the powerdown bit in the PHY Ml serial port Control register. In powerdown mode, the TP outputs are in high impedance state, all functions are disabled except the PHY Ml serial port, and the power consumption is reduced to a minimum.

  • Page 42: Reset

    50 mS after the reset pin was de-asserted or the reset bit is set. Software driver requires to wait for 50mS after setting the RST bit to high to access the internal PHY again. Revision 1.91 (08-18-08) SMSC LAN91C111 REV C DATASHEET...

  • Page 43: Chapter 8 Mac Data Structures And Registers

    BYTE COUNT WORD, the DATA AREA, the CRC, and the CONTROL BYTE. The CRC is not included if the STRIP_CRC bit is set. The maximum number of bytes in a RAM page is 2048 bytes. SMSC LAN91C111 REV C STATUS WORD...

  • Page 44: Receive Frame Status

    CPU, including the source address. The LAN91C111 does not insert its own source address. On receive, all bytes are provided by the CSMA side. The 802.3 Frame Length word (Frame Type in Ethernet) is not interpreted by the LAN91C111. It is treated transparently as data both for transmit and receive operations.

  • Page 45: I/O Space

    The odd byte can be accessed using address (offset + 1). Some registers (like the Interrupt Ack., or like Interrupt Mask) are functionally described as two eight bit registers, in that case the offset of each one is independently specified. SMSC LAN91C111 REV C HASH VALUE 5-0 000 000...

  • Page 46: Bank Select Register

    Note: BANK7 does not exist in LAN91C9x devices. For backward S/W compatibility BANK7 accesses should be done if the Revision Control register indicates the device is the LAN91C111. Revision 1.91 (08-18-08) 10/100 Non-PCI Ethernet Single Chip MAC + PHY Table 8.1 Internal I/O Space Mapping...

  • Page 47: Bank 0 - Transmit Control Register

    10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Bank 7 is a new register Bank to the SMSC LAN91C111 device. This bank has extended registers that allow the extended feature set of the SMSC LAN91C111. Bank 0 - Transmit Control Register...

  • Page 48: Bank 0 - Eph Status Register

    CPU. When TXENA is enabled with no packets in the queue and while the FORCOL bit is set, the LAN91C111 will transmit a preamble pattern the next time a carrier is seen on the line. If a packet is queued, a preamble and SFD will be transmitted. This bit defaults low to normal operation.

  • Page 49: Bank 0 - Receive Control Register

    BYTE SOFT_RST - Software-Activated Reset. Active high. Initiated by writing this bit high and terminated by writing the bit low. The LAN91C111’s configuration is not preserved except for Configuration, Base, and IA0-IA5 Registers. EEPROM is not reloaded after software reset.

  • Page 50: Bank 0 - Counter Register

    ABORT_ENB - Enables abort of receive when collision occurs. Defaults low. When set, the LAN91C111 will automatically abort a packet being received when the appropriate collision input is activated. This bit has no effect if the SWFDUP bit in the TCR is set.

  • Page 51: Bank 0 - Memory Information Register

    DPLX – Duplex Select - This bit selects Full/Half Duplex operation. This bit is valid and selects duplex operation only when the ANEG Bit = 0, this bit overrides the DPLX bit in the PHY Register 0 (Control SMSC LAN91C111 REV C NAME...
  • Page 52 Offset A) DATASHEET Datasheet DUPLEX MODE CONTROL FOR THE 10_FDX 10_HDX SWFDUP Register Register Transmit Control (PHY) (PHY) Register (MAC) DUPLEX MODE CONTROL FOR THE SPEED DPLX SWFDUP Register Register Transmit Control (PHY) (PHY) Register (MAC) SMSC LAN91C111 REV C...
  • Page 53 10 Full Duplex 10 Half Duplex LS2A, LS1A, LS0A – LED select Signal Enable. These bits define what LED control signals are routed to the LEDA output pin on the LAN91C111 Ethernet Controller. The default is 10/100 Link detected. LS2A LS1A LS0A LED SELECT SIGNAL –...

  • Page 54: Bank 1 - Configuration Register

    Host interface however, will still be active allowing the Host access to the device through Standard IO access. All LAN91C111 registers will still be accessible. However, status and control will not be allowed until the EPH Power EN bit is set AND a RESET MMU command is initiated.

  • Page 55: Bank 1 - Base Address Register

    8.12 Bank 1 - Base Address Register OFFSET BASE ADDRESS This register holds the I/O address decode option chosen for the LAN91C111. It is part of the EEPROM saved setup and is not usually modified during run-time. HIGH BYTE BYTE A15 - A13 and A9 - A5 - These bits are compared against the I/O address on the bus to determine the IOBASE for the LAN91C111‘s registers.

  • Page 56: Bank 1 - General Purpose Register

    This register will be used for EEPROM read and write only when the EEPROM SELECT bit in the Control Register is set. This allows generic EEPROM read and write routines that do not affect the basic setup of the LAN91C111. Revision 1.91 (08-18-08)

  • Page 57: Bank 1 - Control Register

    EEPROM status, will NOT have any effect on the internal registers. The CPU can resume accesses to the LAN91C111 after both bits are low. A worst case RELOAD operation initiated by RESET or by software takes less than 750 μs.

  • Page 58: Bank 2 - Mmu Command Register

    Can be used following 3) to release receive packet memory in a more flexible way than 4). Revision 1.91 (08-18-08) 10/100 Non-PCI Ethernet Single Chip MAC + PHY NAME TYPE WRITE ONLY BUSY BIT REGISTER READABLE Reserved Reserved DATASHEET Datasheet SYMBOL MMUCR Reserved Reserved BUSY SMSC LAN91C111 REV C...

  • Page 59: Bank 2 - Packet Number Register

    PACKET NUMBER AT TX AREA - The value written into this register determines which packet number is accessible through the TX area. Some MMU commands use the number stored in this register as the packet number parameter. This register is cleared by a RESET or a RESET MMU Command. SMSC LAN91C111 REV C NAME TYPE...

  • Page 60: Bank 2 - Fifo Ports Register

    Revision 1.91 (08-18-08) 10/100 Non-PCI Ethernet Single Chip MAC + PHY NAME TYPE REGISTER READ ONLY ALLOCATED PACKET NUMBER NAME TYPE READ ONLY RX FIFO PACKET NUMBER TX FIFO PACKET NUMBER DATASHEET Datasheet SYMBOL SYMBOL FIFO SMSC LAN91C111 REV C...

  • Page 61: Bank 2 - Pointer Register

    NOT EMPTY - When set indicates that the Write Data FIFO is not empty yet. The CPU can verify that the FIFO is empty before loading a new pointer value. This is a read only bit. Note: If AUTO INCR. is not set, the pointer must be loaded with a dword aligned value. SMSC LAN91C111 REV C NAME TYPE...

  • Page 62: Bank 2 - Data Register

    This register is mapped into two uni-directional FIFOs that allow moving words to and from the LAN91C111 regardless of whether the pointer address is even, odd or dword aligned. Data goes through the write FIFO into memory, and is pre-fetched from memory into the read FIFO. If byte accesses are used, the appropriate (next) byte can be accessed through the Data Low or Data High registers.
  • Page 63 TXENA cleared - A fatal transmit error occurred forcing TXENA to be cleared. TX_SUC will be low and the specific reason will be reflected by the bits: SQET - SQE Error LOST CARR - Lost Carrier SMSC LAN91C111 REV C NAME TYPE INTERRUPT...
  • Page 64 FIFO PORTS register. The RCV INT bit is always the logic complement of the REMPTY bit in the FIFO PORTS register. Receive Interrupt is cleared when RX FIFO is empty. Revision 1.91 (08-18-08) 10/100 Non-PCI Ethernet Single Chip MAC + PHY DATASHEET Datasheet SMSC LAN91C111 REV C...

  • Page 65: Figure 8.2 Interrupt Structure

    10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Figure 8.2 Interrupt Structure SMSC LAN91C111 REV C Revision 1.91 (08-18-08) DATASHEET...

  • Page 66: Bank 3 - Multicast Table Registers

    10/100 Non-PCI Ethernet Single Chip MAC + PHY NAME TYPE READ/WRITE MULTICAST TABLE 0 MULTICAST TABLE 1 MULTICAST TABLE 2 MULTICAST TABLE 3 MULTICAST TABLE 4 MULTICAST TABLE 5 MULTICAST TABLE 6 MULTICAST TABLE 7 DATASHEET Datasheet SYMBOL SMSC LAN91C111 REV C...

  • Page 67: Bank 3 - Management Interface

    HIGH BYTE CHIP BYTE CHIP - Chip ID. Can be used by software drivers to identify the device used. REV - Revision ID. Incremented for each revision of a given device. SMSC LAN91C111 REV C NAME TYPE MANAGEMENT INTERFACE READ/WRITE...

  • Page 68: Bank 3 - Rcv Register

    MBO - Must be 1. 8.26 Bank 7 - External Registers OFFSET THROUG EXTERNAL REGISTERS nCSOUT is driven low by the LAN91C111 when a valid access to the EXTERNAL REGISTER range occurs. HIGH BYTE BYTE Revision 1.91 (08-18-08) 10/100 Non-PCI Ethernet Single Chip MAC + PHY...
  • Page 69 A3=0 rising edge. A4-15 matches I/O BASE BANK SELECT = 7 BANK SELECT = 4,5,6 High Otherwise High SMSC LAN91C111 REV C LAN91C111 DATA BUS Ignored on writes. Tri-stated on reads. Ignore cycle. Normal LAN91C111 cycle. DATASHEET Revision 1.91 (08-18-08)

  • Page 70: Chapter 9 Phy Mii Registers

    Revision 1.91 (08-18-08) 10/100 Non-PCI Ethernet Single Chip MAC + PHY R/WSC: Read/Write Self Clearing R/LH: Read/Latch high R/LL: Read/Latch REGISTER NAME Control Status PHY ID Auto-Negotiation Advertisement Auto-Negotiation Remote End Capability Reserved Configuration 1 DATASHEET Datasheet SMSC LAN91C111 REV C...

  • Page 71: Table 9.1 Mii Serial Frame Structure

    Read Select 1 = Read Cycle WRITE Write Select 1 = Write Cycle PHYAD[4:0] Physical PHYSICAL ADDRESS Device Address SMSC LAN91C111 REV C REGISTER NAME Configuration 2 Status Output Reserved Table 9.1 MII Serial Frame Structure <PHY Addr.> <REG.Addr.> PHYAD[4:0] REGAD[4:0]...
  • Page 72 D[15:0]... Data These 16 bits contain data to/from one of the eleven registers selected by register address bits REGAD[4:0]. Revision 1.91 (08-18-08) 10/100 Non-PCI Ethernet Single Chip MAC + PHY DATASHEET Datasheet SMSC LAN91C111 REV C...

  • Page 73: Table 9.2 Mii Serial Port Register Map

    10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Table 9.2 MII Serial Port Register MAP SMSC LAN91C111 REV C Revision 1.91 (08-18-08) DATASHEET...

  • Page 74: Register 0. Control Register

    PHY will return a ‘1’ until ANEG is initiated, writing a ‘0’ does not affect the ANEG process. Revision 1.91 (08-18-08) 10/100 Non-PCI Ethernet Single Chip MAC + PHY ANEG_EN MII_DIS Reserved Reserved Reserved DATASHEET Datasheet ANEG_RST DPLX RW. SC Reserved Reserved The internal PHY SMSC LAN91C111 REV C...

  • Page 75: Register 1. Status Register

    When read as ‘1’ indicate ANEG has been completed and that contents in registers 4,5,6 and 7 are valid. ‘0’ means ANEG has not completed and contents in registers 4,5,6 and 7 are meaningless. The PHY returns zero if ANEG is disabled. SMSC LAN91C111 REV C CAP_TF CAP_TH...

  • Page 76: Register 2&3. Phy Identifier Register

    10/100 Non-PCI Ethernet Single Chip MAC + PHY DEFAULT VALUE 0000000000010110 111110 000100 - - - - Reserved Reserved Reserved Reserved DATASHEET Datasheet SOFT RESET Retains Original Value Retains Original Value Retains Original Value Retains Original Value Reserved TX_FDX Reserved Reserved CSMA SMSC LAN91C111 REV C...

  • Page 77: Register 5. Auto-Negotiation Remote End Capability Register

    A '1' indicates the PHY is capable of 802.3 CSMA Operation Register 5. Auto-Negotiation Remote End Capability Register TX_HDX 10_FDX 10_HDX The bit definitions are analogous to the Auto Negotiation Advertisement Register. SMSC LAN91C111 REV C Reserved Reserved Reserved Reserved Reserved...

  • Page 78: Register 16. Configuration 1- Structure And Bit Definition

    0 = Enables AutoNegotiation with devices that transmit unscrambled idle on powerup and various instances Receive Equalizer 1 = Receive Equalizer Disabled, Set To 0 Length DATASHEET Datasheet UNSCDS EQLZR TRF1 TRF0 SMSC LAN91C111 REV C...

  • Page 79: Register 17. Configuration 2 - Structure And Bit Definition

    Reserved Reserved Reserved Reserved Reserved APOLDIS APOLDIS: JABDIS: MREG: SMSC LAN91C111 REV C Select 0 = Receive Equalizer On (For 100MB Mode Only) Cable Type Select 1 = STP (150 Ohm) 0 = UTP (100 Ohm) Receive Input 1 = Receive Squelch Levels Reduced By 4.5 dB R/W...

  • Page 80: Register 18. Status Output - Structure And Bit Definition

    Code Detected On Receive Data 0 = Normal DATASHEET Datasheet 0 = No Multiple Register Access 1 = Interrupt Signaled With MDIO Pulse During Idle 0 = Interrupt Not Signaled On MDIO RPOL R/LT R/LT Reserved Reserved SMSC LAN91C111 REV C...

  • Page 81: Register 19. Mask - Structure And Bit Definition

    Register 19. Mask - Structure and Bit Definition MINT MLNKFAIL MLOSSSYN MSPDDT MDPLDT Reserved MINT: SMSC LAN91C111 REV C Start Of Stream Error 1 = No Start Of Stream Delimiter Detected on Receive Data 0 = Normal End Of Stream Error...

  • Page 82: Register 20. Reserved - Structure And Bit Definition

    For SPDDET In Register 18 0 = No Mask Interrupt Mask Duplex 1 = Mask Interrupt Detect For DPLXDET In Register 18 0 = No Mask Reserved Reserved for Factory Reserved Reserved Reserved DATASHEET Datasheet Reserved Reserved SMSC LAN91C111 REV C...
  • Page 83 10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved:Reserved for Factory Use SMSC LAN91C111 REV C Revision 1.91 (08-18-08) DATASHEET...

  • Page 84: Chapter 10 Software Driver And Hardware Sequence Flow

    The internal PHY entered in powerdown mode, the TP outputs are in high impedance state. Ethernet MAC gates the RX Clock, TX clock derived from the Internal PHY. The EPH Clock is also disabled. DATASHEET Datasheet Table 10.2, the SMSC LAN91C111 REV C...

  • Page 85: Typical Flow Of Events For Transmit (Auto Release = 0)

    Packet Number Register into the TX FIFO. The transmission is now enqueued. No further CPU intervention is needed until a transmit interrupt is generated. SMSC LAN91C111 REV C CONTROLLER FUNCTION Ethernet MAC Enables the RX Clock, TX clock derived from the Internal PHY. The EPH Clock is also enabled.

  • Page 86: Typical Flow Of Events For Transmit (Auto Release = 1)

    The enqueued packet will be transferred to the MAC block as a function of TXENA (nTCR) bit and of the deferral process (1/2 duplex mode only) state. Transmit pages are released by transmit completion. DATASHEET Datasheet SMSC LAN91C111 REV C...

  • Page 87: Typical Flow Of Event For Receive

    REMOVE AND RELEASE FROM TOP OF RX command to have the MMU free up the used memory and packet number. SMSC LAN91C111 REV C MAC SIDE The MAC generates a TXEMPTY interrupt upon a completion of a sequence of enqueued packets.

  • Page 88: Figure 10.1 Interrupt Service Routine

    Call EPH INTR Return Buffers to Upper Layer Disable Allocation Interrupt MDINT? Mask Restore Address Pointer & Bank Select Registers Call MDINT Unmask SMC91C111 Interrupts Exit ISR Figure 10.1 Interrupt Service Routine Revision 1.91 (08-18-08) SMSC LAN91C111 REV C DATASHEET...

  • Page 89: Figure 10.2 Rx Intr

    10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet SMSC LAN91C111 REV C RX INTR Write Ad. Ptr. Reg. & Read Word 0 from RAM Destination Multicast? Read Words 2, 3, 4 from RAM for Address Filtering Address Filtering Pass?

  • Page 90: Figure 10.3 Tx Intr

    Write (0x00A0, (Bank2, Offset 0)); //Option 2: Re-Enqueue the packet Write (0x00C0, (Bank2, Offset 0)); Temp = Read(Bank0, Offset 0); Temp = Temp2 OR 0x0001 Write (Temp2, (Bank 0, Offset 0)); Figure 10.3 TX INTR DATASHEET Datasheet SMSC LAN91C111 REV C...

  • Page 91: Figure 10.4 Txempty Intr (Assumes Auto Release Option Selected)

    TXEMPTY = 0 & TXINT = 0 (Waiting for Completion) Figure 10.4 TXEMPTY INTR (Assumes Auto Release Option Selected) SMSC LAN91C111 REV C TXEMPTY INTR Write Acknowledge Reg. with TXEMPTY Bit Set Read TXEMPTY & TX INTR TXEMPTY = 1 TXEMPTY = X &...

  • Page 92: Figure 10.5 Drive Send And Allocate Routines

    Figure 10.5 Drive Send and Allocate Routines MEMORY PARTITIONING Unlike other controllers, the LAN91C111 does not require a fixed memory partitioning between transmit and receive resources. The MMU allocates and de-allocates memory upon different events. An additional mechanism allows the CPU to prevent the receive process from starving the transmit memory allocation.
  • Page 93 TX FIFO PACKET NUMBER at the FIFO PORTS register. This eliminates the need for the driver to keep a list of packet numbers being transmitted. The numbers are queued by the LAN91C111 and provided back to the CPU as their transmission completes.

  • Page 94: Figure 10.6 Interrupt Generation For Transmit, Receive, Mmu

    TX EMPTY OPTIONS ALLOC 'EMPTY' RX PACKET NUMBER 'NOT EMPTY' TX DONE PACKET NUMBER CSMA ADDRESS CPU ADDRESS M.S. BIT ONLY PACK # OUT Figure 10.6 Interrupt Generation for Transmit, Receive, MMU Revision 1.91 (08-18-08) SMSC LAN91C111 REV C DATASHEET...

  • Page 95: Chapter 11 Board Setup Information

    In order to support a software utility based installation, even if the EEPROM was never programmed, the EEPROM can be written using the LAN91C111. One of the IOS combination is associated with a fixed default value for the key parameters (I/O BASE) that can always be used regardless of the EEPROM based value being programmed.
  • Page 96 STORE and RELOAD bits of CTR will readback as both bits high. No other bits of the LAN91C111 can be read or written until the EEPROM operation completes and both bits are clear. This mechanism is also valid for reset initiated reloads.

  • Page 97: Figure 11.1 64 X 16 Serial Eeprom Map

    10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet IOS2-0 WORD ADDRESS Figure 11.1 64 X 16 Serial EEPROM Map SMSC LAN91C111 REV C 16 BITS CONFIGURATION REG. BASE REG. CONFIGURATION REG. BASE REG. CONFIGURATION REG. BASE REG. CONFIGURATION REG.

  • Page 98: Chapter 12 Application Considerations

    VL Local Bus 32 Bit Systems On VL Local Bus and other 32 bit embedded systems the LAN91C111 is accessed as a 32 bit peripheral in terms of the bus interface. All registers except the DATA REGISTER will be accessed using byte or word instructions.
  • Page 99 SIGNAL D0-D31 D0-D31 nLDEV nLDEV nRD nWR A1 nVLBUS OPEN nDATCS SMSC LAN91C111 REV C NOTES 32 bit data bus. The bus byte(s) used to access the device are a function of nBE0-nBE3: nBE0 nBE1 nBE2 nBE3 Double word access Not used = tri-state on reads, ignored on writes.

  • Page 100: Figure 12.1 Lan91C111 On Vl Bus

    HIGH-END ISA OR NON-BURST EISA MACHINES On ISA machines, the LAN91C111 is accessed as a 16 bit peripheral. The signal connections are listed in the following table: Table 12.2 High-End ISA or Non-Burst EISA Machines Signal Connectors ISA BUS...
  • Page 101 W/nR, nRDYRTN, LCLK SMSC LAN91C111 REV C NOTES I/O Write strobe - asynchronous write access. Address is valid before leading edge. Data is latched on trailing edge. This signal is negated on leading nRD, nWR if necessary. It is then asserted on CLK rising edge after the access condition is satisfied.

  • Page 102: Figure 12.2 Lan91C111 On Isa Bus

    EISA 32 BIT SLAVE On EISA the LAN91C111 is accessed as a 32 bit I/O slave, along with a Slave DMA type "C" data path option. As an I/O slave, the LAN91C111 uses asynchronous accesses. In creating nRD and nWR inputs, the timing information is externally derived from nCMD edges.
  • Page 103 Not used = tri-state on reads, ignored on writes. Note that nBE2 and nBE3 override the value of A1, which is tied low in this application. Other combinations of nBE are not supported by the LAN91C111. Software drivers are not anticipated to generate them.

  • Page 104: Figure 12.3 Lan91C111 On Eisa Bus

    LATCH nCMD gates BCLK nSTART nEX32 Revision 1.91 (08-18-08) 10/100 Non-PCI Ethernet Single Chip MAC + PHY NOTES A2-A15 RESET D0-D31 INTR0 LAN91C111 nBE[0:3] LCLK nADS nLDEV O.C. Figure 12.3 LAN91C111 on EISA BUS DATASHEET Datasheet SMSC LAN91C111 REV C...

  • Page 105: Chapter 13 Operational Description

    High Input Level IHIS Schmitt Trigger Hysteresis Input Buffer Low Input Level ILCK High Input Level IHCK SMSC LAN91C111 REV C 0°C to +70°C for LAN91C111 (-40°C to 85°C for LAN91C111I) -55C° to + 150°C +325°C + 0.3V -0.3V DATASHEET UNITS COMMENTS...
  • Page 106 = -4 mA = 0 to V = 20 mA = -10 mA = 0 to V = 35 mA = -15 mA = 0 to V = 35 mA = -15 mA = 0 to V SMSC LAN91C111 REV C...
  • Page 107 PARAMETER SYMBOL Clock Input Capacitance Input Capacitance Output Capacitance CAPACITIVE LOAD ON OUTPUTS ARDY, D0-D31 (non VLBUS) D0-D31 in VLBUS All other outputs SMSC LAN91C111 REV C = 3.3V LIMITS 45 pF 45 pF 45 pF DATASHEET UNITS COMMENTS = 35 mA = -15 mA µA...

  • Page 108: Twisted Pair Characteristics, Transmit

    100 Mbps, Output Data=scrambled /H/ 100 Mbps 10 Mbps 10 Mbps 10 Mbps, NLP and FLP 10 Mbps. 100 Mbps, UTP with TLVL[3:0]=1000 100 Mbps, STP with TLVL[3:0]=1000 10 Mbps, UTP with TLVL[3:0]=1000 10 Mbps, STP with TLVL[3:0]=1000 SMSC LAN91C111 REV C...

  • Page 109: Twisted Pair Characteristics, Receive

    TP Input Common Mode Voltage Range TP Input Differential Voltage Range TP Input Resistance TP Input Capacitance SMSC LAN91C111 REV C UNIT CONDITIONS VDD = 3.3V, Adjustable with RBIAS, relative to TOIA with RBIAS=11K 1.16 VDD = 3.3V, Adjustable with LVL[3:0]...

  • Page 110: Chapter 14 Timing Diagrams

    High to Data Invalid Data Setup to nWR Inactive Data Hold After nWR Inactive nRD Strobe Width Revision 1.91 (08-18-08) 10/100 Non-PCI Ethernet Single Chip MAC + PHY Valid t6 t6 Valid DATASHEET Datasheet Valid UNITS SMSC LAN91C111 REV C...

  • Page 111: Figure 14.2 Asynchronous Cycle - Using Nads

    Data Setup to nWR Inactive Data Hold After nWR Inactive nRD Strobe Width A1-A15, AEN, nBE[3:0] Setup to nADS Rising A1-A15, AEN, nBE[3:0] Hold after nADS Rising SMSC LAN91C111 REV C 50ns 100ns 150ns Asynchronous Cycle -- Using nADS valid...

  • Page 112: Figure 14.3 Asynchronous Cycle - Nads=0

    Revision 1.91 (08-18-08) 10/100 Non-PCI Ethernet Single Chip MAC + PHY 100ns 150ns Asynchronous Cycle - nADS=0 valid D0~D31 valid Valid Address Valid Figure 14.4 Asynchronous Ready DATASHEET Datasheet 200ns 250n UNITS Valid Address Valid Data SMSC LAN91C111 REV C...

  • Page 113: Figure 14.5 Burst Write Cycles - Nvlbus=1

    W/nR Hold After LCLK Falling Data Setup to LCLK Rising (Write) Data Hold from LCLK Rising (Write) nCYCLE Setup to LCLK Rising t22A nCYCLE Hold After LCLK Rising SMSC LAN91C111 REV C DATASHEET UNITS t12A t17A t22A UNITS Revision 1.91 (08-18-08)

  • Page 114: Figure 14.6 Burst Read Cycles - Nvlbus=1

    Hold after LCLK Falling W/nR Setup to LCLK Falling t17A W/nR Hold After LCLK Falling Data Delay from LCLK Rising (Read) Revision 1.91 (08-18-08) 10/100 Non-PCI Ethernet Single Chip MAC + PHY DATASHEET Datasheet t12A t17A UNITS SMSC LAN91C111 REV C...

  • Page 115: Figure 14.7 Address Latching For All Modes

    A1-A15, AEN, nBE[3:0] Hold After nADS Rising A4-A15, AEN to nLDEV Delay Clock Address, AEN, nBE[3:0] nADS W/nR nCYCLE Write Data nSRDY Figure 14.8 Synchronous Write Cycle - nVLBUS=0 SMSC LAN91C111 REV C Valid Valid DATASHEET UNITS t17A Valid Revision 1.91 (08-18-08)

  • Page 116: Figure 14.9 Synchronous Read Cycle - Nvlbus=0

    Delay from LCLK Rising Clock Address, AEN, nBE[3:0] nADS W/nR nCYCLE Read Data nSRDY nRDYRTN Figure 14.9 Synchronous Read Cycle - nVLBUS=0 Revision 1.91 (08-18-08) 10/100 Non-PCI Ethernet Single Chip MAC + PHY Valid DATASHEET Datasheet UNITS Valid SMSC LAN91C111 REV C...

  • Page 117: Figure 14.10Mii Timing

    TXEN100 RXD0-RXD3 RX25 RX_DV RX_ER PARAMETER TXD0-TXD3, TXEN100 Delay from TX25 Rising RXD0-RXD3, RX_DV, RX_ER Setup to RX25 Rising RXD0-RXD3, RX_DV, RX_ER Hold After RX25 Rising SMSC LAN91C111 REV C Figure 14.10 MII Timing DATASHEET UNITS UNITS Revision 1.91 (08-18-08)

  • Page 118: Figure 14.11Transmit Timing

    ±5.5 4500 /J/K/ DATA t 31 PREAMBLE PREAMBLE DATA t 35 Figure 14.11 Transmit Timing DATASHEET Datasheet UNIT CONDITIONS 100Mbps 10Mbps nS pk-pk 100Mbps nS pk-pk 10Mbps 10Mbps 10Mbps /T/R/ IDLE t 33 t 32 DATA SMSC LAN91C111 REV C...

  • Page 119: Figure 14.12Receive Timing, End Of Packet - 10 Mbps

    Assert Time Xmt Packet Start to COL Assert Time Start of Packet to Transmit JAM Packet Start During JAM Xmt Packet Start to COL Assert Time SMSC LAN91C111 REV C LIMIT UNIT ±3.0 nS pk-pk ±13.5 nS pk-pk t 37...

  • Page 120: Figure 14.13Collision Timing, Receive

    DATA DATA DATA DATA DATA Collision Observed by Physical Layer t 34 Collision Observed by Physical Layer t 34 Figure 14.13 Collision Timing, Receive DATASHEET Datasheet DATA DATA DATA DATA DATA DATA t 35 t 35 SMSC LAN91C111 REV C...

  • Page 121: Figure 14.14Collision Timing, Transmit

    Datasheet MII 100 Mbps TPI± DATA DATA TPO± LEDn MII 10 Mbps TPI± TPO± LEDn Figure 14.14 Collision Timing, Transmit SMSC LAN91C111 REV C DATA DATA DATA DATA DATA DATA DATA DATA DATA Collision Observed by Physical Layer t 34...

  • Page 122: Figure 14.15Jam Timing

    Revision 1.91 (08-18-08) 10/100 Non-PCI Ethernet Single Chip MAC + PHY DATA DATA DATA DATA DATA DATA DATA DATA t 41 Collision Observed by Physical Layer Figure 14.15 Jam Timing DATASHEET Datasheet DATA DATA DATA DATA SMSC LAN91C111 REV C...

  • Page 123: Table 14.4 Link Pulse Timing Characteristics

    FLP Receive Link Pulse Burst Minimum Period Required For Detection FLP Receive Link Pulse Burst Maximum Period Required For Detection FLP Receive Link Pulses Bursts Required To Detect AutoNegotiation Capability SMSC LAN91C111 REV C LIMIT UNIT Figure 7.8 Link Pulses μS 55.5...

  • Page 124: Figure 14.16Link Pulse Timing

    10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet TPO± t 42 t 43 a.) Transmit NLP TPI± t 44 t 45 t 47 t 46 LEDn b.) Receive NLP Figure 14.16 Link Pulse Timing Revision 1.91 (08-18-08) SMSC LAN91C111 REV C DATASHEET...

  • Page 125: Figure 14.17Flp Link Pulse Timing

    Transmit FLP and Transmit FLP Burst TPI± 31.25 t 52 t 53 t 55 t 56 TPI± t 57 LEDn SMSC LAN91C111 REV C DATA t 51 DATA 62.5 93.75 t 54 b.) Receive FLP t 58 c.) Receive FLP Burst Figure 14.17 FLP Link Pulse Timing...

  • Page 126: Chapter 15 Package Outlines

    0.20 Lead Frame Thickness 0.75 Lead Foot Length from Centerline Lead Length Lead Pitch Lead Foot Angle 0.23 Lead Width Lead Shoulder Radius 0.20 Lead Foot Radius 0.0762 Coplanarity (Assemblers) 0.08 Coplanarity (Test House) DATASHEET Datasheet SMSC LAN91C111 REV C...

  • Page 127: Figure 15.2 128 Pin Qfp Package Outline, 3.9 Mm Footprint

    4. Dimension for foot length L measured at the gauge plane 0.25 mm above the seating plane. 5. Details of pin 1 identifier are optional but must be located within the zone indicated. SMSC LAN91C111 REV C REMARKS Overall Package Height Standoff 3.05...

  • Page 128: Chapter 16 Revision History

    Fixed commercial temp range to state “0°C to +70°C for LAN91C111” Added bullet: “Commercial Temperature Range from 0°C to 70°C (LAN91C111)” Changed REV default from “0001” to “0010” Changed T1A time in table under figure from 10nS min to 2nS min.

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