SMSC LAN9500 Specification Sheet
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SMSC LAN9500 Specification Sheet

Hi-speed usb 2.0 to 10/100 ethernet controller
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PRODUCT FEATURES

Highlights
Single Chip Hi-Speed USB 2.0 to 10/100 Ethernet
Controller
Integrated 10/100 Ethernet MAC with Full-Duplex
Support
Integrated 10/100 Ethernet PHY with HP Auto-MDIX
support
Integrated USB 2.0 Hi-Speed Device Controller
Integrated USB 2.0 Hi-Speed PHY
Implements Reduced Power Operating Modes
Target Applications
Embedded Systems
Set-Top Boxes
PVR's
CE Devices
Networked Printers
USB Port Replicators
Standalone USB to Ethernet Dongles
Test Instrumentation
Industrial
Key Benefits
USB Device Controller
— Fully compliant with Hi-Speed Universal Serial Bus
Specification Revision 2.0
— Supports HS (480 Mbps) and FS (12 Mbps) modes
— Four endpoints supported
— Supports vendor specific commands
— Integrated USB 2.0 PHY
— Remote wakeup supported
High-Performance 10/100 Ethernet Controller
— Fully compliant with IEEE802.3/802.3u
— Integrated Ethernet MAC and PHY
— 10BASE-T and 100BASE-TX support
— Full- and half-duplex support
— Full- and half-duplex flow control
SMSC LAN9500/LAN9500i
LAN9500/LAN9500i
Hi-Speed USB 2.0 to 10/100
Ethernet Controller
— Preamble generation and removal
— Automatic 32-bit CRC generation and checking
— Automatic payload padding and pad removal
— Loop-back modes
— TCP/UDP/IP/ICMP checksum offload support
— Flexible address filtering modes
– One 48-bit perfect address
– 64 hash-filtered multicast addresses
– Pass all multicast
– Promiscuous mode
– Inverse filtering
– Pass all incoming with status report
— Wakeup packet support
— Integrated Ethernet PHY
– Auto-negotiation
– Automatic polarity detection and correction
– HP Auto-MDIX support
– Link status change wake-up detection
— Support for 3 status LEDs
— External MII and Turbo MII support HomePNA™ and
HomePlug® PHY
Power and I/Os
— Various low power modes
— 11 GPIOs
— Supports bus-powered and self-powered operation
— Integrated power-on reset circuit
— External 3.3v I/O supply
– Internal 1.8v core supply regulator
Miscellaneous Features
— EEPROM Controller
— IEEE 1149.1 (JTAG) Boundary Scan
— Requires single 25 MHz crystal
Software
— Windows XP/Vista Driver
— Linux Driver
— Win CE Driver
— MAC OS Driver
— EEPROM Utility
Packaging
— 56-pin QFN (8x8 mm) Lead-Free RoHS Compliant
package
Environmental
— Commercial Temperature Range (0°C to +70°C)
— Industrial Temperature Range (-40°C to +85°C)
DATASHEET
Datasheet
Revision 1.7 (10-02-08)

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Summary of Contents for SMSC LAN9500

  • Page 1: Product Features

    — Fully compliant with IEEE802.3/802.3u — Integrated Ethernet MAC and PHY — 10BASE-T and 100BASE-TX support — Full- and half-duplex support — Full- and half-duplex flow control SMSC LAN9500/LAN9500i LAN9500/LAN9500i Hi-Speed USB 2.0 to 10/100 Ethernet Controller — Preamble generation and removal —...
  • Page 2 Any and all such uses without prior written approval of an Officer of SMSC and further testing and/or modification will be fully at the risk of the customer. Copies of this document or other SMSC literature, as well as the Terms of Sale Agreement, may be obtained by visiting SMSC’s website at http://www.smsc.com.

  • Page 3: Table Of Contents

    Chapter 6 Revision History ........... 42 SMSC LAN9500/LAN9500i DATASHEET Revision 1.7 (10-02-08)
  • Page 4 Figure 1.1 LAN9500/LAN9500i System Diagram ......... . . 6 Figure 2.1 LAN9500/LAN9500i 56-QFN Pin Assignments (TOP VIEW)......9 Figure 4.1 Output Equivalent Test Load .
  • Page 5 Table 4.14 LAN9500/LAN9500i Crystal Specifications ........

  • Page 6: Chapter 1 Introduction

    1.1.1 Overview The LAN9500/LAN9500i is a high performance Hi-Speed USB 2.0 to 10/100 Ethernet controller. With applications ranging from embedded systems, set-top boxes, and PVR’s, to USB port replicators, USB to Ethernet dongles, and test instrumentation, the LAN9500/LAN9500i is a high performance and cost competitive USB to Ethernet connectivity solution.

  • Page 7: Usb

    Hi-Speed USB 2.0 to 10/100 Ethernet Controller Datasheet 1.1.2 The USB portion of the LAN9500/LAN9500i integrates a Hi-Speed USB 2.0 device controller and USB PHY. The USB device controller contains a USB low-level protocol interpreter which implements the USB bus protocol, packet generation/extraction, PID/Device ID parsing, and CRC coding/decoding, with autonomous error handling.

  • Page 8: Eeprom Controller

    1.1.6 EEPROM Controller The LAN9500/LAN9500i contains an EEPROM controller for connection to an external EEPROM. This allows for the automatic loading of static configuration data upon power-on reset, pin reset, or software reset. The EEPROM can be configured to load USB descriptors, USB device configuration, and MAC address.

  • Page 9: Chapter 2 Pin Description And Configuration

    TXD0/GPIO4/EEP_DISABLE NOTE: When HP Auto-MDIX is activated, the TXN/TXP pins can function as RXN/RXP and vice-versa NOTE: Exposed pad (VSS) on bottom of package must be connected to ground Figure 2.1 LAN9500/LAN9500i 56-QFN Pin Assignments (TOP VIEW) SMSC LAN9500/LAN9500i SMSC...
  • Page 10 (PD) external PHY. GPIO1 IS/O8/ General Purpose I/O 1 (PU) Management Clock: In external PHY mode, this pin outputs the management clock to the external (PD) PHY. GPIO2 IS/O8/ General Purpose I/O 2 (PU) DATASHEET Datasheet DESCRIPTION SMSC LAN9500/LAN9500i...
  • Page 11 (Internal PHY Mode Only) USB Port PORT_SWAP Swap Configuration Strap SMSC LAN9500/LAN9500i Table 2.1 MII Interface Pins (continued) BUFFER TYPE TXD3 Transmit Data 3: In external PHY mode, this pin functions as the transmit data 3 output to the (PU) external PHY.
  • Page 12 Transmit Clock: In external PHY mode, this pin is the transmitter clock input from the external (PU) PHY. In internal PHY mode, this pin is not used. DATASHEET Datasheet DESCRIPTION for more information on for more information on SMSC LAN9500/LAN9500i...

  • Page 13: Table 2.2 Eeprom Pins

    EEPROM. (PD) Power Select Configuration Strap: Determines the default power setting when no EEPROM is (PD) present. 0 = The LAN9500/LAN9500i is bus powered. 1 = The LAN9500/LAN9500i is self powered. Note 2.2 configuration straps. Table 2.3 JTAG Pins BUFFER...

  • Page 14: Table 2.4 Miscellaneous Pins

    (PU) the Ethernet link is operating in full-duplex mode. GPIO8 IS/O12/ General Purpose I/O 8 OD12 Note: (PU) DATASHEET Hi-Speed USB 2.0 to 10/100 Ethernet Controller Datasheet DESCRIPTION DESCRIPTION By default this pin is configured as a GPIO. SMSC LAN9500/LAN9500i...
  • Page 15 Detect VBUS_DET Upstream VBUS Power Test 1 Test 2 Test 3 SMSC LAN9500/LAN9500i BUFFER TYPE OD12 Ethernet Link Activity Indicator LED (Active- Low): This signal is driven low (LED on) when a (PU) valid link is detected. This pin is pulsed high (LED off) for 80mS whenever transmit or receive activity is detected.

  • Page 16: Table 2.5 Usb Pins

    Connect to an external 12K 1.0% resistor to ground. USB PLL +1.8V Supply: This pin must be connected to VDD18CORE for proper operation. Refer to the LAN9500/LAN9500i reference schematic for additional connection information. ICLK Crystal Input: External 25 MHz crystal input.

  • Page 17: Table 2.7 I/O Power Pins, Core Power Pins, And Ground Pad

    (PU) external PHY and indicates a PHY interrupt has occurred. VDD33A +3.3V Analog Power Supply Refer to the LAN9500/LAN9500i reference schematic for connection information. EXRES External PHY Bias Resistor: Used for the internal bias circuits. Connect to an external 12.4K 1.0% resistor to ground.

  • Page 18: Table 2.9 56-Qfn Package Pin Assignments

    TDI/RXD3 GPIO8 nLNKA_LED/ RXCLK GPIO9 nSPD_LED/ RXDV GPIO10 EXPOSED PAD MUST BE CONNECTED TO VSS DATASHEET Datasheet PIN NAME TXEN RXER CRS/GPIO3 COL/GPIO0 TXCLK VDD33IO TEST1 VDD18CORE VDD33IO VDD33IO TXD3/GPIO7/ EEP_SIZE TXD2/GPIO6/ PORT_SWAP TXD1/GPIO5/ RMT_WKP TXD0/GPIO4/ EEP_DISABLE SMSC LAN9500/LAN9500i...

  • Page 19: Buffer Types

    Note: Internal pull-down resistors prevent unconnected inputs from floating. Do not rely on internal resistors to drive signals external to the LAN9500/LAN9500i. When connected to a load that must be pulled low, an external resistor must be added. Analog input...

  • Page 20: Chapter 3 Eeprom Controller (Epc)

    Note the EEPROM offsets are given in units of 16-bit word offsets. A length field with a value of zero indicates that the field does not exist in the EEPROM. The LAN9500/LAN9500i will use the field’s HW default value in this case.

  • Page 21: Table 3.2 Configuration Flags Description

    RESERVED Power Method SMSC LAN9500/LAN9500i Table 3.1 EEPROM Format (continued) DESCRIPTION 0 = LAN9500/LAN9500i does not support remote wakeup. 1 = LAN9500/LAN9500i supports remote wakeup. 0 = LAN9500/LAN9500i is bus powered. 1 = LAN9500/LAN9500i is self powered. DATASHEET Revision 1.7 (10-02-08)

  • Page 22: Eeprom Defaults

    Certain system level resets (USB reset, POR, nRESET, and SRST) cause the EEPROM contents to be loaded into LAN9500/LAN9500i. After a reset, the EEPROM controller attempts to read the first byte of data from the EEPROM. If the value 0xA5 is read from the first address, then the EEPROM controller will assume that an external Serial EEPROM is present.

  • Page 23: An Example Of Eeprom Format Interpretation

    0070h 0078h 0080h 0088h 0090h - 00FFh SMSC LAN9500/LAN9500i provide an example of how the contents of a EEPROM are formatted. Table 3.4 Dump of EEPROM Memory VALUE A5 12 34 56 78 9A BC 01 04 04 09 04 0A 0F 10 14...

  • Page 24: Table 3.5 Eeprom Example - 256 Byte Eeprom

    MAC Address 12 34 56 78 9A BC Full-Speed Polling Interval for Interrupt Endpoint (1ms) Hi-Speed Polling Interval for Interrupt Endpoint (4ms) Configuration Flags - LAN9500/LAN9500i is bus powered and supports remote wakeup. Language ID Descriptor 0409h, English Manufacturer ID String Descriptor Length (10 bytes)
  • Page 25 Manufacturer ID String (“SMSC” in UNICODE) Size of Product Name String Descriptor (16 bytes) Descriptor Type (String Descriptor - 03h) Product Name String (“LAN9500” in UNICODE) Size of Serial Number String Descriptor (16 bytes) Descriptor Type (String Descriptor - 03h) Serial Number String (“0005123”...
  • Page 26 Value to use as an argument to select this configuration Index of String Descriptor describing this configuration Bus powered and remote wakeup enabled Maximum Power Consumption is 500 mA Size of Full-Speed Interface Descriptor in Bytes (9 Bytes) DATASHEET Datasheet SMSC LAN9500/LAN9500i...
  • Page 27 Table 3.5 EEPROM Example - 256 Byte EEPROM (continued) EEPROM EEPROM CONTENTS ADDRESS (HEX) 90h- FFh SMSC LAN9500/LAN9500i DESCRIPTION Descriptor Type (Interface Descriptor - 04h) Number identifying this Interface Value used to select alternative setting Number of Endpoints used for this interface (Less endpoint 0) Class Code...

  • Page 28: Chapter 4 Operational Characteristics

    Supply Voltage (VDD33A, VDD33BIAS, VDD33IO) ......+3.3V +/- 300mV Ambient Operating Temperature in Still Air (T **Proper operation of LAN9500/LAN9500i is guaranteed only within the ranges specified in this section. Revision 1.7 (10-02-08) Hi-Speed USB 2.0 to 10/100 Ethernet Controller...

  • Page 29: Power Consumption

    Datasheet Power Consumption This section details the power consumption of LAN9500/LAN9500i as measured during various modes of operation. Power consumption values are provided for both the device-only, and for the device plus Ethernet components. Power dissipation is determined by temperature, supply voltage, and external source/sink requirements.

  • Page 30: Operational Power Consumption

    Customer Evaluation Board Operational Power Consumption Table 4.5 Customer Evaluation Board Operational Power Consumption - Supply and Current @3.3V PARAMETER 100BASE-TX Full Duplex (USB High-Speed) Total SMSC Customer Evaluation Board Current Consumption Revision 1.7 (10-02-08) Hi-Speed USB 2.0 to 10/100 Ethernet Controller TYPICAL 137.3...

  • Page 31: Dc Specifications

    ICLK Type Buffer (XI Input) Low Input Level High Input Level Note 4.5 This specification applies to all inputs and tri-stated bi-directional pins. Internal pull-down and pull-up resistors add +/- 50uA per-pin (typical). SMSC LAN9500/LAN9500i Table 4.6 I/O Buffer Characteristics -0.3 1.01 1.18 1.35 1.39...

  • Page 32: Table 4.7 100Base-Tx Transceiver Characteristics

    Revision 1.7 (10-02-08) Hi-Speed USB 2.0 to 10/100 Ethernet Controller SYMBOL 1050 -950 -1050 SYMBOL DATASHEET Datasheet UNITS NOTES mVpk Note 4.8 mVpk Note 4.8 Note 4.8 Note 4.8 Note 4.8 Note 4.9 Note 4.10 UNITS NOTES Note 4.11 SMSC LAN9500/LAN9500i...

  • Page 33: Ac Specifications

    Hi-Speed USB 2.0 to 10/100 Ethernet Controller Datasheet AC Specifications This section details the various AC timing specifications of the LAN9500/LAN9500i. Note: The MII timing adheres to the IEEE 802.3 specification. Refer to the IEEE 802.3 specification for detailed MII timing information.

  • Page 34: Power-On Configuration Strap Valid Timing

    VDD33IO 2.0V Configuration Straps Figure 4.2 Power-On Configuration Strap Valid Timing Table 4.9 Power-On Configuration Strap Valid Timing SYMBOL DESCRIPTION UNITS Configuration strap valid time Revision 1.7 (10-02-08) SMSC LAN9500/LAN9500i DATASHEET...

  • Page 35: Reset And Configuration Strap Timing

    SYMBOL nRESET input assertion time rstia Configuration strap pins setup to nRESET deassertion Configuration strap pins hold after nRESET deassertion Output drive after deassertion odad SMSC LAN9500/LAN9500i rstia odad Figure 4.3 nRESET Reset Pin Timing DESCRIPTION DATASHEET UNITS Revision 1.7 (10-02-08)

  • Page 36: Eeprom Timing

    4.5.4 EEPROM Timing The following specifies the EEPROM timing requirements for LAN9500/LAN9500i: EECS cshckh EECLK EEDO EEDI EEDI (VERIFY) SYMBOL DESCRIPTION EECLK Cycle time ckcyc EECLK High time EECLK Low time EECS high before rising edge of EECLK cshckh EECLK falling edge to EECS low...

  • Page 37: Turbo Mii Interface Timing

    Note 4.12 These values satisfy the MII specification requirement of 0 ns to 25 ns clock to output delay. Note 4.13 Timing was designed for system load between 5 pf and 15 pf. RXCLK RXD[3:0] RXDV SMSC LAN9500/LAN9500i txhold Figure 4.1 Turbo MII Output Timing rxhold rxsetup Figure 4.2 Turbo MII Input Timing...

  • Page 38: Table 4.13 Turbo Mii Interface Timing Values

    Note 4.14 These values satisfy the 10-ns setup and hold time requirements that are necessary for the Turbo MII specification. Revision 1.7 (10-02-08) Hi-Speed USB 2.0 to 10/100 Ethernet Controller DATASHEET Datasheet UNITS NOTES Note 4.14 Note 4.14 SMSC LAN9500/LAN9500i...

  • Page 39: Clock Circuit

    Datasheet Clock Circuit LAN9500/LAN9500i can accept either a 25MHz crystal (preferred) or a 25MHz single-ended clock oscillator (+/- 50ppm) input. If the single-ended clock oscillator method is implemented, XO should be left unconnected and XI should be driven with a nominal 0-3.3V clock signal. The input clock duty cycle is 40% minimum, 50% typical and 60% maximum.

  • Page 40: Chapter 5 Package Outline

    Chapter 5 Package Outline Figure 5.1 LAN9500/LAN9500i 56-QFN Package Table 5.1 LAN9500/LAN9500i 56-QFN Dimensions NOMINAL 0.70 0.00 0.02 7.85 8.00 D1/E1 7.55 D2/E2 5.75 5.90 0.30 0.18 0.25 0.50 BSC Notes: 1. All dimensions are in millimeters unless otherwise noted.

  • Page 41: Figure 5.2 Lan9500/Lan9500I 56-Qfn Recommended Pcb Land Pattern

    Hi-Speed USB 2.0 to 10/100 Ethernet Controller Datasheet Figure 5.2 LAN9500/LAN9500i 56-QFN Recommended PCB Land Pattern SMSC LAN9500/LAN9500i Revision 1.7 (10-02-08) DATASHEET...

  • Page 42: Chapter 6 Revision History

    Chapter 2, "Pin Description and Configuration," on page 9 Chapter 2, "Pin Description and Configuration," on page 9 Rev. 1.2 Table 4.14, “LAN9500/LAN9500i Crystal Specifications,” on page 39 (06-16-08) Rev. 1.2 Table 2.9, “56-QFN Package Pin Assignments,” on page 18 (06-10-08) Table 2.8, “No-Connect Pins,”...

  • Page 43: Table 6.2 Datasheet Revision History (Internal)

    Table 6.1 Customer Revision History (continued) REVISION LEVEL AND DATE SECTION/FIGURE/ENTRY Table 2.4, “Miscellaneous Pins,” on page 14 Figure 2.1 LAN9500/LAN9500i 56- QFN Pin Assignments (TOP VIEW) on page 9 Table 2.1, “MII Interface Pins,” on page 10 Pins,” on page 13 Note 2.1 on page 12...

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