SMSC LAN9420 Datasheet
  1. Manuals
  2. Brands
  3. SMSC Manuals
  4. Controller
  5. LAN9420
  6. Datasheet

SMSC LAN9420 Datasheet

Single-chip ethernet controller with hp auto-mdix support and pci interface
Hide thumbs
Table of Contents

Advertisement

Quick Links

Download this manual

PRODUCT FEATURES

Highlights
Optimized for embedded applications with 32-bit
RISC CPUs
Integrated descriptor based scatter-gather DMA and
IRQ deassertion timer effectively increase network
throughput and reduce CPU loading
Integrated Ethernet MAC with full-duplex support
Integrated 10/100 Ethernet PHY with HP Auto-MDIX
support
32-bit, 33MHz, PCI 3.0 compliant interface
Reduced power operating modes with PCI Power
Management Specification 1.1 compliance
Supports multiple audio & video streams over
Ethernet
Target Applications
Cable, satellite, and IP set-top boxes
Digital televisions
Digital video recorders
Home gateways
Digital media clients/servers
Industrial automation systems
Industrial/single board PC
Kiosk/POS enterprise equipment
Key Benefits
Integrated High-Performance 10/100 Ethernet
Controller
— Fully compliant with IEEE802.3/802.3u
— Integrated Ethernet MAC and PHY
— 10BASE-T and 100BASE-TX support
— Full- and half-duplex support
— Full-duplex flow control
— Preamble generation and removal
— Automatic 32-bit CRC generation and checking
— Automatic payload padding and pad removal
— Loop-back modes
— Flexible address filtering modes
– One 48-bit perfect address
– 64 hash-filtered multicast addresses
– Pass all multicast
SMSC LAN9420/LAN9420i
LAN9420/LAN9420i
Single-Chip Ethernet Controller
with HP Auto-MDIX Support
and PCI Interface
– Promiscuous mode
– Inverse filtering
– Pass all incoming with status report
— Wakeup packet support
— Integrated 10/100 Ethernet PHY
– Auto-negotiation
– Automatic polarity detection and correction
– Supports HP Auto-MDIX
– Supports energy-detect power down
— Support for 3 status LEDs
— Receive and transmit TCP checksum offload
PCI Interface
— PCI Local Bus Specification Revision 3.0 compliant
— 32-bit/33-MHz PCI bus
— Descriptor based scatter-gather DMA enables zero-
copy drivers
Comprehensive Power Management Features
— Supports PCI Bus Power Management Interface
Specification, Revision 1.1
— Supports optional wake from D3cold
(via configuration strap option when Vaux is available)
— Wake on LAN
— Wake on link status change (energy detect)
— Magic packet wakeup
General Purpose I/O
— 3 programmable GPIO pins
— 2 GPO pins
Support for Optional EEPROM
— Serial interface provided for EEPROM
— Used to store PCI and MAC address configuration
values
Miscellaneous Features
— Big/Little/Mixed endian support for registers,
descriptors, and buffers
— IRQ deassertion timer
— General purpose timer
Single 3.3V Power Supply
— Integrated 1.8V regulator
Packaging
— Available in 128-pin VTQFP Lead-free RoHS Compliant
package
Environmental
— Available in commercial & industrial temperature ranges
DATASHEET
Datasheet
Revision 1.22 (09-25-08)

Advertisement

Table of Contents
loading
Need help?

Need help?

Do you have a question about the LAN9420 and is the answer not in the manual?

Questions and answers

Subscribe to Our Youtube Channel

Related Manuals for SMSC LAN9420

Summary of Contents for SMSC LAN9420

  • Page 1: Product Features

    — Automatic payload padding and pad removal — Loop-back modes — Flexible address filtering modes – One 48-bit perfect address – 64 hash-filtered multicast addresses – Pass all multicast SMSC LAN9420/LAN9420i LAN9420/LAN9420i Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface – Promiscuous mode –...
  • Page 2 Any and all such uses without prior written approval of an Officer of SMSC and further testing and/or modification will be fully at the risk of the customer. Copies of this document or other SMSC literature, as well as the Terms of Sale Agreement, may be obtained by visiting SMSC’s website at http://www.smsc.com.

  • Page 3: Table Of Contents

    DMA Controller Architecture ..........38 SMSC LAN9420/LAN9420i DATASHEET Revision 1.22 (09-25-08)
  • Page 4 Auto-negotiation ............70 Revision 1.22 (09-25-08) Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface DATASHEET Datasheet SMSC LAN9420/LAN9420i...
  • Page 5 Bus Mode Register (BUS_MODE)......... 104 SMSC LAN9420/LAN9420i G3 ...
  • Page 6 PCI Clock Timing ............. 162 Revision 1.22 (09-25-08) Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface DATASHEET Datasheet SMSC LAN9420/LAN9420i...
  • Page 7 Chapter 7 Revision History ..........169 SMSC LAN9420/LAN9420i DATASHEET Revision 1.22 (09-25-08)
  • Page 8 Figure 2.1 LAN9420/LAN9420i 128-VTQFP (Top View)........
  • Page 9 Table 5.12 EEPROM Timing Values ........... . 165 SMSC LAN9420/LAN9420i Revision 1.22 (09-25-08)
  • Page 10 Table 6.1 LAN9420/LAN9420i 128-VTQFP Dimensions ........

  • Page 11: Chapter 1 Introduction

    Status Registers Interrupt Power System Control & Controller Management Status Registers (INT) (PM) LAN9420/LAN9420i Figure 1.2 LAN9420/LAN9420i Internal Block Diagram SMSC LAN9420/LAN9420i LAN9420/LAN9420i External PCI Device 25MHz Crystal PCI Device Figure 1.1 System Level Block Diagram Ethernet MAC TX DMA Engine...

  • Page 12: General Description

    These include a multipurpose 16-bit configurable General Purpose Timer (GPT), a Free-Run Counter, a 3-pin configurable GPIO/LED interface, and 2 GPO pins. All aspects of LAN9420/LAN9420i are managed via a set of memory mapped control and status registers.

  • Page 13: Pci Bridge

    LAN9420/LAN9420i implements a PCI Local Bus Specification Revision 3.0 compliant interface, supporting the PCI Bus Power Management Interface Specification Revision 1.1. It provides the PCI Configuration Space Control and Status registers used to configure LAN9420/LAN9420i for PCI device operation. Please refer to...

  • Page 14: Pll And Power Management

    30 for more information. 1.7.6 Free Run Counter The Free Run Counter has no dedicated function within LAN9420/LAN9420i and may be used by the software drivers as a timebase. Please refer to for more information. Control and Status Registers (CSR) LAN9420/LAN9420i’s functions are controlled and monitored by the Host via the Control and Status...

  • Page 15: Chapter 2 Pin Description And Configuration

    VDD33A EXRES VDD33BIAS AUTOMDIX_EN VDD18TX VDD18PLL PWRGOOD VAUXDET GPIO0/nLED1 NOTE: When HP Auto-MDIX is activated, the TPO+/- pins function as TPI+/- and vice-versa. Figure 2.1 LAN9420/LAN9420i 128-VTQFP (Top View) SMSC LAN9420/LAN9420i SMSC LAN9420/LAN9420i 128-VTQFP TOP VIEW DATASHEET AD15 nCBE1 nSERR...

  • Page 16: Pin List

    PCI Auxiliary Voltage Sense: This pin is used to sense (PD) the presence of a 3.3V auxiliary supply in order to define the PME support available. Note: This pin is pulled low through an internal pull- down resistor DATASHEET Datasheet DESCRIPTION SMSC LAN9420/LAN9420i...

  • Page 17: Table 2.2 Eeprom

    PCInRST following power up. The “IS” input buffer type is enabled only during power up. The “IS” input buffer type is disabled at all other times. SMSC LAN9420/LAN9420i Table 2.2 EEPROM BUFFER...

  • Page 18: Table 2.3 Gpio And Led Pins

    (Link & Activity Indicator): This pin can also function as the Ethernet Link and Activity Indicator LED and is driven low (LED on) when LAN9420/LAN9420i detects a valid link. This pin is pulsed high (LED off) for 80mS whenever transmit or receive activity is detected.

  • Page 19: Table 2.5 Pll And Ethernet Phy Pins

    TPI+ Data In Positive External EXRES PHY Bias Resistor SMSC LAN9420/LAN9420i Table 2.5 PLL and Ethernet PHY Pins BUFFER TYPE ICLK Crystal Input: External 25MHz crystal input. This pin can also be driven by a single-ended clock oscillator. When this method is used, XO should be left unconnected.

  • Page 20: Table 2.6 Power And Ground Pins

    Table 2.6 Power and Ground Pins BUFFER TYPE +3.3V Analog Power Supply Refer to the LAN9420/LAN9420i application note for connection information. +1.8V PLL Power Supply: This pin must be connected to VDD18CORE for proper operation. Refer to the LAN9420/LAN9420i application note for additional connection information.

  • Page 21: Table 2.8 128-Vtqfp Package Pin Assignments

    VDD18CORE VDD33IO nINT PCInRST PCICLK nGNT nREQ nPME VDD33IO AD31 AD30 AD29 AD28 AD27 VDD33IO AD26 AD25 AD24 SMSC LAN9420/LAN9420i PIN NAME PIN NAME nCBE3 AD14 IDSEL VDD33IO VDD33IO AD13 AD23 AD12 AD22 AD11 AD21 AD10 AD20 AD19 VDD33IO VDD33IO...

  • Page 22: Buffer Types

    Note: Internal pull-up resistors prevent unconnected inputs from floating. Do not rely on internal resistors to drive signals external to LAN9420/LAN9420i. When connected to a load that must be pulled high, an external resistor must be added. 50uA (typical) internal pull-down. Unless otherwise noted in the pin description, internal pull- downs are always enabled.

  • Page 23: Chapter 3 Functional Description

    Figure 1.2 LAN9420/LAN9420i Internal Block Diagram on page PCI Bridge (PCIB) The PCI Bridge (PCIB) facilitates LAN9420/LAN9420i’s operation on a PCI bus as a device. It has the following features: PCI Master Interface: This interface connects LAN9420/LAN9420i to the PCI bus when it is functioning as a PCI Master.

  • Page 24: Pci Bridge (Pcib) Block Diagram

    To/From DMAC Arbiter PCI Master To/From CSR Blocks PM Related Signals PCI Target (To/From PM) Configuration Space CSR PM Signal (From PM) nPME PME Gating nINT Interrupt Gating Figure 3.1 PCI Bridge Block Diagram Revision 1.22 (09-25-08) SMSC LAN9420/LAN9420i DATASHEET...

  • Page 25: Pci Interface Environments

    The PCIB supports only Device operation. It functions as a simple bridge, permitting LAN9420/LAN9420i to act as a master/target PCI device on the PCI bus. The Host performs PCI arbitration and is responsible for initializing configuration space for all devices on the bus.

  • Page 26: Pci Target Interface

    The Host initializes and configures the PCI Device during a plug-and-play process. The PCI Target Interface supports 32-bit slave accesses only. Non 32-bit PCI target reads to LAN9420/LAN9420i will result in a full 32-bit read. Non 32-bit PCI target writes to LAN9420/LAN9420i will be silently discarded.

  • Page 27: I/O Mapping Of Csr

    3.2.4.4 PCI Discard Timer When the PCI master performs a read of LAN9420/LAN9420i, the PCI Bridge will fetch the data and acknowledge the PCI transfer when data is available. If the PCI master malfunctions and does complete the transaction within 32768 PCI clocks, LAN9420/LAN9420i will flush the data to prevent a potential bus lock-up.

  • Page 28: System Control Block (Scb)

    MAC address, PCI Subsystem ID, and PCI Subsystem Vendor ID. In addition, it may also be used for general data storage. The EEPROM controller provides LAN9420/LAN9420i access to the EEPROM and permits the Host to read, write and erase its contents.

  • Page 29: Figure 3.6 Interrupt Controller Block Diagram

    Registers (SCSR) block. The interrupt status register (INT_STS) reflects the current state of the interrupt sources prior to qualification with their associated enables. The SW_INT, MBERR_INT, SBERR_INT, GPIOx_INT, and GPT_INT are latched, and are cleared through the SCSR block upon a SMSC LAN9420/LAN9420i Figure 3.6 Interrupt Controller...

  • Page 30: Wake Event Detection Logic

    MAC wakeup event (Wakeup Frame or Magic Packet), or on an Ethernet link status change (energy detect). Note: LAN9420/LAN9420i can optionally generate a PCI interrupt in addition to assertion of nPME on detection of a power management event. Generation of a PCI interrupt is not the typical usage.

  • Page 31: Free-Run Counter (Frc)

    When the FRC reaches a value of FFFF_FFFFh, it wraps around to 0000_0000h and continues counting. The FRC is operational in all power states. The FRC has no fixed function in LAN9420/LAN9420i and is ideal for use by drivers as a timebase. The current FRC count is readable in FREE_RUN SCSR. Please refer to for more information on this register.

  • Page 32: Mac Address, Subsystem Id, And Subsystem Vendor Id Auto-Load

    The signature value of 0xA5 is stored at address 0. A different signature value indicates to the EEPROM controller that no EEPROM or an un-programmed EEPROM is attached to LAN9420/LAN9420i. In this case, following default values are used for the Subsystem Device ID (SSID), Subsystem Vendor ID (SSVID), and the MAC address.

  • Page 33: Supported Eeprom Operations

    EEPROM, the Host must first issue the EWEN command. If an operation is attempted, and an EEPROM device does not respond within 30mS, LAN9420/LAN9420i will timeout, and the EPC Time-out bit (EPC_TO) in the E2P_CMD register will be set.

  • Page 34: Figure 3.8 Eeprom Erase Cycle

    ERAL (Erase All): If erase/write operations are enabled in the EEPROM, this command will initiate a bulk erase of the entire EEPROM.The EPC_TO bit is set if the EEPROM does not respond within 30ms. EECS EECLK EEDIO (OUTPUT) EEDIO (INPUT) Figure 3.9 EEPROM ERAL Cycle Revision 1.22 (09-25-08) SMSC LAN9420/LAN9420i DATASHEET...

  • Page 35: Figure 3.10 Eeprom Ewds Cycle

    Note: The EEPROM device will power-up in the erase/write-disabled state. Any erase or write operations will fail until an Erase/Write Enable command is issued. EECS EECLK EEDIO (OUTPUT) EEDIO (INPUT) SMSC LAN9420/LAN9420i Figure 3.10 EEPROM EWDS Cycle Figure 3.11 EEPROM EWEN Cycle DATASHEET Revision 1.22 (09-25-08)

  • Page 36: Figure 3.12 Eeprom Read Cycle

    E2P_DATA register to be written to the EEPROM location selected by the EPC Address field (EPC_ADDR). The EPC_TO bit is set if the EEPROM does not respond within 30ms. EECS EECLK EEDIO (OUTPUT) EEDIO (INPUT) Figure 3.13 EEPROM WRITE Cycle Revision 1.22 (09-25-08) SMSC LAN9420/LAN9420i DATASHEET...

  • Page 37: Host Initiated Mac Address, Ssid, Ssvid Reload

    Supported EEPROM operations are described in these sections. 3.3.5.3.4 EEPROM TIMING Refer to Section 5.8, "EEPROM Timing," on page 165 SMSC LAN9420/LAN9420i Figure 3.14 EEPROM WRAL Cycle Cycles", shown below, shows the number of EECLK cycles required for Table 3.4 Required EECLK Cycles REQUIRED EECLK CYCLES for a detailed description of these registers.

  • Page 38: System Control And Status Registers (Scsr)

    DMA Control and Status Registers (DCSR), as described in Registers (DCSR)," on page Revision 1.22 (09-25-08) Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Section 4.3, "DMAC Control and Status 103. DATASHEET Datasheet for a complete SMSC LAN9420/LAN9420i...
  • Page 39 The DMAC will skip to the next frame buffer when end of frame is detected. Data chaining can be enabled or disabled. The ring and chain type descriptor structures are illustrated in Note: Descriptors of zero buffer length are not supported at the initial and final descriptors of a chain. SMSC LAN9420/LAN9420i DATASHEET Figure 3.15.

  • Page 40: Figure 3.15 Ring And Chain Descriptor Structures

    Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface BUFFER 1 DESCRIPTOR 0 BUFFER 2 BUFFER 1 DESCRIPTOR 1 BUFFER 2 BUFFER 1 DESCRIPTOR n BUFFER 2 BUFFER 1 DESCRIPTOR 0 BUFFER 1 DESCRIPTOR 1 NEXT DESCRIPTOR DATASHEET Datasheet SMSC LAN9420/LAN9420i...

  • Page 41: Receive Descriptors

    (LS) bit is set and the received frame is greater than or equal to 64 bytes in length. Host Actions: Checks this bit to determine status. DMAC Actions: Sets/clears this bit to define status. SMSC LAN9420/LAN9420i ES DE LE RF MF FS LS TL CS FT RW ME DB CE R...
  • Page 42 Host Actions: Checks this bit to determine status. DMAC Actions: Sets/clears this bit to define status. Revision 1.22 (09-25-08) Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Table 3.5 RDES0 Bit Fields (continued) DESCRIPTION DATASHEET Datasheet SMSC LAN9420/LAN9420i...
  • Page 43 DMAC Actions: Sets/clears this bit to define status. RESERVED Host Actions: Cleared on writes and ignored on reads. DMAC Actions: Ignored on reads and cleared on writes. SMSC LAN9420/LAN9420i Table 3.5 RDES0 Bit Fields (continued) DESCRIPTION DATASHEET Revision 1.22 (09-25-08)

  • Page 44: Table 3.6 Rdes1 Bit Fields

    DMAC Actions: Reads this field upon opening a new DMA descriptor to obtain the buffer address. Revision 1.22 (09-25-08) Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Table 3.6 RDES1 Bit Fields DESCRIPTION (RX_BASE_ADDR). Table 3.7 RDES2 Bit Fields DESCRIPTION DATASHEET Datasheet Receive List SMSC LAN9420/LAN9420i...

  • Page 45: Transmit Descriptors

    TDES3 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SMSC LAN9420/LAN9420i Table 3.8 RDES3 Bit Fields...

  • Page 46: Table 3.9 Tdes0 Bit Fields

    64 bytes. Host Actions: Checks this bit to determine status. DMAC Actions: Sets/clears this bit to define status. Revision 1.22 (09-25-08) Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Table 3.9 TDES0 Bit Fields DESCRIPTION DATASHEET Datasheet SMSC LAN9420/LAN9420i...

  • Page 47: Table 3.10 Tdes1 Bit Fields

    When set, indicates that the buffer contains the first segment of a frame. Host Actions: Initializes this bit. DMAC Actions: Reads this bit to determine whether the buffer contains the first segment of a frame. SMSC LAN9420/LAN9420i Table 3.9 TDES0 Bit Fields (continued) DESCRIPTION Table 3.10 TDES1 Bit Fields...
  • Page 48 DMAC Actions: Reads this field to determine the allocated size of associated data buffer. Revision 1.22 (09-25-08) Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Table 3.10 TDES1 Bit Fields (continued) DESCRIPTION DATASHEET Datasheet Section 3.5.6, "Transmit Transmit List Base SMSC LAN9420/LAN9420i...

  • Page 49: Initialization

    The receive and transmit engines begin processing receive and transmit operations. 5. Set bit 2 (RXEN) of MAC_CR to turn the receiver on. 6. Set bit 3 (TXEN) of MAC_CR to turn the transmitter on. SMSC LAN9420/LAN9420i Table 3.11 TDES2 Bit Fields DESCRIPTION Table 3.12 TDES3 Bit Fields...

  • Page 50: Transmit Operation

    Descriptor acquisition is attempted if any of the following conditions are satisfied: When the (SR) Start/Stop Receive bit (bit 1 of DMAC_CONTROL) sets immediately after being placed in the running state Revision 1.22 (09-25-08) Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface DATASHEET Datasheet SMSC LAN9420/LAN9420i...

  • Page 51: Suspend State Behavior

    RX DMA). Performing these steps in the reverse order will result in RX DMA not stopping (DMAC_STATUS will continue to show the Receive Process State (RS) as Running and Receive Process Stopped (RPS) does not assert). SMSC LAN9420/LAN9420i DATASHEET Revision 1.22 (09-25-08)

  • Page 52: Tx Buffer Fragmentation Rules

    2KB - 3 DWORDs (2,036 bytes total). Any transmit packet that is so highly fragmented that it takes more space than this must be un-fragmented (by copying to a driver-supplied buffer) before the transmit packet can be sent to LAN9420/LAN9420i. One approach to determine whether a packet is too fragmented is to calculate the actual amount of space that it will consume, and check it against 2,036 bytes.

  • Page 53: 10/100 Ethernet Mac

    These features include the ability to disable retries after a collision, dynamic FCS (Frame Check Sequence) generation on a frame-by-frame basis, automatic pad field insertion and deletion to enforce minimum frame size attributes, and automatic SMSC LAN9420/LAN9420i DATASHEET Revision 1.22 (09-25-08)

  • Page 54: Flow Control

    On the backend, the MAC interfaces with the 10/100 PHY through an MII (Media Independent Interface) port which is internal to LAN9420/LAN9420i. The MCSR also provide a mechanism for accessing the PHY’s internal registers through the internal SMI (Serial Management Interface) bus.

  • Page 55: Address Filtering Functional Description

    Section 4.4.1, "MAC Control Register (MAC_CR)," on page If the frame fails the filter, the MAC does not receive the packet. The Host has the option of accepting or ignoring the packet. MCPAS PRMS INVFILT SMSC LAN9420/LAN9420i Ethernet frame (1518 BYTES) SOURCE ADDR. TYPE (6 BYTES)

  • Page 56: Perfect Filtering

    Pass all multicast frames. Frames with physical addresses are hash- filtered Section 4.4.2, "MAC Address High Section 4.4.3, "MAC Section 125) and multicast hash table low (refer 126) in the MCSR to form a 123) and the MAC address 124). If the SMSC LAN9420/LAN9420i...

  • Page 57: Wakeup Frame Detection

    Note 3.1 Wakeup frame detection can be performed when LAN9420/LAN9420i is in any power state. Wakeup frame detection is enabled when the WUEN bit is set. Note: When wake-up frame detection is enabled via the WUEN bit of the...

  • Page 58: Table 3.15 Filter I Byte Mask Bit Definitions

    3.15, describes the byte mask’s bit fields. FILTER i BYTE MASK DESCRIPTION FILTER i COMMANDS Table 3.17 describes the Filter i Offset bit fields. Table 3.17 Filter i Offset Bit Definitions FILTER i OFFSET DESCRIPTION DATASHEET Datasheet Table 3.16 shows the Filter I command SMSC LAN9420/LAN9420i...

  • Page 59: Magic Packet Detection

    Magic Packet pattern. It checks only packets with the MAC’s address or a broadcast address to meet the Magic Packet requirement. The MAC checks each received frame for the pattern 48’hFF_FF_FF_FF_FF_FF after the destination and source address field. SMSC LAN9420/LAN9420i Table 3.18 Filter i CRC-16 Bit Definitions FILTER i CRC-16 DESCRIPTION is set.

  • Page 60: Receive Checksum Offload Engine (Rxcoe)

    00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 …CRC It should be noted that Magic Packet detection can be performed when LAN9420/LAN9420i is in any power management state.

  • Page 61: Figure 3.20 Type Ii Ethernet Frame

    Datasheet Example frame configurations: Figure 3.21 Ethernet Frame with VLAN Tag {DSAP, SSAP, CTRL, OUI[23:16]} Figure 3.22 Ethernet Frame with Length Field and SNAP Header SMSC LAN9420/LAN9420i L3 Packet Calculate Checksum Figure 3.20 Type II Ethernet Frame L3 Packet Calculate Checksum...

  • Page 62: Figure 3.23 Ethernet Frame With Vlan Tag And Snap Header

    Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface {OUI[15:0], PID[15:0]} L3 Packet Calculate Checksum {OUI[15:0], PID[15:0]} L3 Packet Calculate Checksum Checksum Offload Engine Control Register (COE_CR) (MAC_CR)) and vice versa. These functions cannot be enabled DATASHEET Datasheet enables the SMSC LAN9420/LAN9420i...

  • Page 63: Rx Checksum Calculation

    The TX checksum cannot be inserted in the MAC header (first 14 bytes) or in the last 4 bytes of the TX packet. 15:12 RESERVED SMSC LAN9420/LAN9420i Table 3.20). The TX checksum preamble instructs the TXCOE on Table 3.20 TX Checksum Preamble...

  • Page 64: Tx Checksum Calculation

    Section 4.4, "MAC Control and Status Registers (MCSR)," on page 118 description of the MCSR. 10/100 Ethernet PHY LAN9420/LAN9420i integrates an IEEE 802.3 Physical Layer for Twisted Pair Ethernet applications (PHY). The PHY can be configured for either 100 Mbps (100BASE-TX) or 10 Mbps (10BASE-T) Ethernet operation.

  • Page 65: 100Base-Tx Transmit

    The encoding process may be bypassed by clearing bit 6 of register 31. When the encoding is bypassed, the 5 transmit data bit is equivalent to TX_ER. CODE GROUP 11110 01001 10100 10101 01010 01011 01110 01111 SMSC LAN9420/LAN9420i 100M 4B/5B 25MHz by 4 bits Encoder 125 Mbps Serial MLT-3 MLT-3 MLT-3 Converter Driver MLT-3 CAT-5 Figure 3.25 100BASE-TX Data Path...

  • Page 66: Scrambling

    Sent for rising TX_EN Sent for falling TX_EN Sent for falling TX_EN Sent for rising TX_ER INVALID INVALID INVALID INVALID INVALID INVALID INVALID INVALID INVALID INVALID DATASHEET Datasheet TRANSMITTER INTERPRETATION 1000 1001 1010 1011 1100 1101 1110 1111 SMSC LAN9420/LAN9420i...

  • Page 67: Nrzi And Mlt3 Encoding

    Equalizer, Baseline Wander Correction and Clock and Data Recovery The 6 bits from the ADC are fed into the DSP block. The equalizer in the DSP section compensates for phase and amplitude distortion caused by the physical channel consisting of magnetics, connectors, SMSC LAN9420/LAN9420i 100M 25MHz...

  • Page 68: Nrzi And Mlt-3 Decoding

    SSD error), RX_ER is asserted and the value 1110b is driven onto the internal receive data bus (RXD) to the MAC. Note that the internal MII’s data valid signal (RX_DV) is not yet asserted when the bad SSD occurs. Revision 1.22 (09-25-08) Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface DATASHEET Datasheet SMSC LAN9420/LAN9420i...

  • Page 69: 10Base-T Transmit

    The polarity of the signal is also checked. If the polarity is reversed (local TPI+ is connected to TPI- of the remote partner and vice versa), then this is identified and corrected. The reversed condition SMSC LAN9420/LAN9420i DATASHEET Revision 1.22 (09-25-08)

  • Page 70: Jabber Detection

    The 16 even-numbered pulses, which may be present or absent, contain the data word being transmitted. Presence of a data pulse represents a “1”, while absence represents a “0”. Revision 1.22 (09-25-08) Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface DATASHEET Datasheet SMSC LAN9420/LAN9420i...

  • Page 71: Datasheet

    3.6.6 Parallel Detection If LAN9420/LAN9420i is connected to a device lacking the ability to auto-negotiate (i.e. no FLPs are detected), it is able to determine the speed of the link based on either 100M MLT-3 symbols or 10M Normal Link Pulses. In this case the link is presumed to be half-duplex per the IEEE standard. This ability is known as “Parallel Detection”.

  • Page 72: Half Vs. Full-Duplex

    If a user plugs in either a direct connect LAN cable, or a cross-over patch cable, as shown in LAN9420/LAN9420i Auto-MDIX PHY is capable of configuring the TPO+/TPO- and TPI+/TPI- twisted pair pins for correct transceiver operation.

  • Page 73: Energy Detect Power-Down

    LA N94 2 0/ LA N9 42 0i s up po r ts t he m an da t or y D 0, D3 LAN9420/LAN9420i can signal a wake event detection by asserting the nPME pin. The nPME signal can be generated in all states, including (optionally) the D3 SMSC LAN9420/LAN9420i for additional information on this register.

  • Page 74: Related External Signals And Power Supplies

    As a result of the nPME assertion by the device, the PCI Host can reconfigure the power management state. This mechanism is used, for example, when LAN9420/LAN9420i is in low power mode and must be restored to a functional state, as a result of the detection of “Wake On LAN” event. The Host can...

  • Page 75: Device Clocking

    Internally, LAN9420/LAN9420i generates its required clocks with a phase-locked loop (PLL). The LAN9420/LAN9420i reduces its power consumption in the D3 state by disabling its internal PLL and derivative clocks. The 25MHz clock remains operational in all states where power is applied.

  • Page 76: Exiting The G3 State

    (PCInRST=X, PM_STATE=X, VAUXDET=0, PWRGOOD=0) and then 3.3Vaux is applied (PCInRST=0, PM_STATE=X, VAUXDET=0 to 1, PWRGOOD=0). LAN9420/LAN9420i detects the application of auxiliary power and asserts its internal power-on reset (POR). POR resets the and Status Register (PCI_PMCSR) PCI Power Management Control and Status Register (PCI_PMCSR) internal PHY is held in the general-power down state and the device is powered by the PCI 3.3Vaux...

  • Page 77: Exiting The D0A State

    Management Control and Status Register (PCI_PMCSR) VAUXDET=X, PWRGOOD=1). A D3 Transition Reset (D3RST) occurs during this transition. Refer Section 3.7.5, "Resets," on page 79 SMSC LAN9420/LAN9420i Section 3.7.6, "Detecting Power Management Events," on page 80 state under the following conditions. State transitions are illustrated in Power Management State (PM_STATE) (PCI_PMCSR).

  • Page 78: The D3Cold State

    State COLD LAN9420/LAN9420i’s behavior in this state is dependant on the status of VAUXDET. When VAUXDET=0, LAN9420/LAN9420i is powered from the system’s +3.3V supply; wake from D3 disabled and the PCI +3.3V power supply is off. Since VAUXDET=0, the device is powered from the system’s +3.3V power supply and LAN9420/LAN9420i loses all power and context (to...

  • Page 79: Resets

    (except PME registers) TX/RX DMACS SCSR Note 3.6 PME logic is reset by PCInRST if LAN9420/LAN9420i is not configured to support D3 wake; PME logic is not reset by PCInRST if LAN9420/LAN9420i is configured to support wake. COLD Note 3.7 Software Reset does not clear control register bits marked as NASR.

  • Page 80: Phy Resets

    3.7.6 Detecting Power Management Events LAN9420/LAN9420i supports the ability to generate PCI wake events using nPME on detection of a Magic Packet, Wakeup Frame or Ethernet link status change (energy detect). A simplified diagram of the wake event detection logic is shown in...

  • Page 81: Enabling Wakeup Frame Wake Events

    3.7.6.1 Enabling Wakeup Frame Wake Events The Host system must perform the following steps to enable LAN9420/LAN9420i to assert a PCI wake event (nPME) on detection of a Wakeup frame. 1. All transmit and receive operations must be halted: a.
  • Page 82 Power Management State (PM_STATE) . Device behavior in this state is described in PME Enable (PME_EN) and/or the DATASHEET Datasheet Power Management Control Register field to 11b (‘D3’ state). The Section 3.7.4.4, "The D3HOT PME Status (PME_STATUS) bits are SMSC LAN9420/LAN9420i...

  • Page 83: Chapter 4 Register Descriptions

    In the case of BAR3, BA may be either the address of the lower (for little endian access) or upper (for big endian access) 512 byte segment of the 1KB MemSpace. See Mapping on page 27 for details. SMSC LAN9420/LAN9420i Figure 3.3 CSR Double Endian DATASHEET for details.

  • Page 84: Figure 4.1 Lan9420/Lan9420I Csr Memory Map

    B A + 7 C h B A + 5 8 h B A + 5 4 h Figure 4.1 LAN9420/LAN9420i CSR Memory Map Revision 1.22 (09-25-08) Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface N o te : B A R 3 –...

  • Page 85: Register Nomenclature

    Unless otherwise noted, do not read from or write to reserved addresses. Register attribute examples: R/W: Can be written. Will return current setting on a read. R/WC: Will return current setting on a read. Writing a one clears the bit. SMSC LAN9420/LAN9420i Table 4.1 Register Bit Types REGISTER BIT DESCRIPTION DATASHEET...

  • Page 86: System Control And Status Registers (Scsr)

    General Purpose Timer Current Count BUS_CFG System Bus Configuration Register PMT_CTRL Power Management Control RESERVED Reserved for Future Use FREE_RUN Free Run Counter E2P_CMD EEPROM Command Register E2P_DATA EEPROM Data Register RESERVED Reserved for Future Use DATASHEET Datasheet REGISTER NAME SMSC LAN9420/LAN9420i...

  • Page 87: Id And Revision (Id_Rev)

    This 16-bit field is used to identify the device model. 15:0 Block Revision. This 16-bit field is used to identify the revision of the Ethernet Subsystem. Note 4.1 Default value is dependent on device revision. SMSC LAN9420/LAN9420i 00C0h Size: 32 bits DESCRIPTION DATASHEET...

  • Page 88: Interrupt Control Register (Int_Ctl)

    When set high, wake event detection is enabled as an interrupt source. RESERVED Revision 1.22 (09-25-08) Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface 00C4h Size: 32 bits Section 3.3.1, "Interrupt Controller," on DESCRIPTION DATASHEET Datasheet TYPE DEFAULT 000b SMSC LAN9420/LAN9420i...

  • Page 89: Interrupt Status Register (Int_Sts)

    Slave Bus Error Interrupt (SBERR_INT) When set, indicates that the PCI Target Interface has detected an error when the Host attempted to access the LAN9420/LAN9420i CSR. The interrupt is cleared by writing a ‘1’ to this bit. Writing a ‘0’ has no effect.
  • Page 90 DMA interrupt is cleared by clearing the interrupt source in the DMAC_STATUS DCSR. Writing to this bit has no effect. Revision 1.22 (09-25-08) Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface DESCRIPTION Power (PMT_CTRL). Both WUPS bits must be DATASHEET Datasheet TYPE DEFAULT SMSC LAN9420/LAN9420i...

  • Page 91: Interrupt Configuration Register (Int_Cfg)

    INT_DEAS field, any subsequent interrupts will obey the new setting. Note: The interrupt de-assertion interval does not apply to the wake interrupt. SMSC LAN9420/LAN9420i 00CCh Size: for more information on the Interrupt Controller. DESCRIPTION DATASHEET 32 bits Section 3.3.1, "Interrupt...

  • Page 92: General Purpose Input/Output Configuration Register (Gpio_Cfg)

    GPIO0 – bit 16 GPIO1 – bit 17 GPIO2 – bit 18 15:11 RESERVED Revision 1.22 (09-25-08) Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface 00D0h Size: 32 bits DESCRIPTION DATASHEET Datasheet TYPE DEFAULT 000b 000b 000b 000b SMSC LAN9420/LAN9420i...

  • Page 93: Table 4.3 Eeprom Enable Bit Definitions

    GPIO1 – bit 1 GPIO2 – bit 2 Note 4.2 Default value is dependent on the state of the GPIO pin. Table 4.3 EEPROM Enable Bit Definitions [22] [21] [20] SMSC LAN9420/LAN9420i DESCRIPTION EEDIO FUNCTION EEDIO GPO3 Reserved GPO3 Reserved...

  • Page 94: General Purpose Timer Configuration Register (Gpt_Cfg)

    Timer (GPT)," on page 30 Revision 1.22 (09-25-08) Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface 00D4h Size: Section 3.3.3, "General Purpose Timer (GPT)," DESCRIPTION Section 3.3.3, "General Purpose for more details. DATASHEET Datasheet 32 bits TYPE DEFAULT FFFFh SMSC LAN9420/LAN9420i...

  • Page 95: General Purpose Timer Current Count Register (Gpt_Cnt)

    This register reflects the current value of the general purpose timer. BITS 31:16 RESERVED 15:0 General Purpose Timer Current Count (GPT_CNT) This 16-bit field reflects the current value of the GPT. SMSC LAN9420/LAN9420i 00D8h Size: 32 bits DESCRIPTION DATASHEET TYPE...

  • Page 96: Bus Master Bridge Configuration Register (Bus_Cfg)

    This field has no effect unless the BAR bit in the BUS_MODE DCSR is cleared. Setting Priority Ratio (RX:TX) ------------------------------------------------ 24:0 RESERVED Revision 1.22 (09-25-08) Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface 00DCh Size: DESCRIPTION DATASHEET Datasheet 32 bits TYPE DEFAULT SMSC LAN9420/LAN9420i...

  • Page 97: Power Management Control Register (Pmt_Ctrl)

    1xb – MAC wakeup event (Wakeup Frame or Magic Packet) Note: If waking from a reduced-power state causes the assertion of a device reset, the wakeup status bits will be cleared. RESERVED SMSC LAN9420/LAN9420i 00E0h Size: 32 bits DESCRIPTION DATASHEET...

  • Page 98: Free Run Counter (Free_Run)

    Refer to 3.3.4, "Free-Run Counter (FRC)," on page 31 FRC. Revision 1.22 (09-25-08) Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface 00F4h Size: 32 bits DESCRIPTION for more information on the DATASHEET Datasheet TYPE DEFAULT Section SMSC LAN9420/LAN9420i...

  • Page 99: Eeprom Command Register (E2P_Cmd)

    EPC busy will be high immediately following power-up or reset. After the EEPROM controller has finished reading (or attempting to read) the MAC address and SSVID/SSID from the EEPROM, the EPC Busy bit is cleared. SMSC LAN9420/LAN9420i 00F8h Size: 32 bits...
  • Page 100 WRAL commands are the only EPC commands that will time- out if an EEPROM device is not present -and- the EEDIO signal is pulled low. Revision 1.22 (09-25-08) Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface DESCRIPTION DATASHEET Datasheet TYPE DEFAULT 000b R/WC SMSC LAN9420/LAN9420i...
  • Page 101 RELOAD command has completed. EPC Address (EPC_ADDR) The 8-bit value in this field is used by the EEPROM Controller to address the specific memory location in the Serial EEPROM. This is a Byte aligned address. SMSC LAN9420/LAN9420i DESCRIPTION DATASHEET TYPE DEFAULT R/WC Revision 1.22 (09-25-08)

  • Page 102: Eeprom Data Register (E2P_Data)

    EEPROM controller during auto-loading, or the last value read during an attempt to auto- load the EEPROM contents. Revision 1.22 (09-25-08) Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface 00FCh Size: 32 bits DESCRIPTION DATASHEET Datasheet TYPE DEFAULT Note 4.3 SMSC LAN9420/LAN9420i...

  • Page 103: Dmac Control And Status Registers (Dcsr)

    0024h – 004Ch RESERVED 0050h CUR_TX_BUF_ADDR 0054h CUR_RX_BUF_ADDR 0058h – 007Ch RESERVED SMSC LAN9420/LAN9420i SYMBOL Bus Mode Register Transmit Poll Demand Register Receive Poll Demand Register Receive List Base Address Register Transmit List Base Address Register DMA Controller Status Register...

  • Page 104: Bus Mode Register (Bus_Mode)

    Note: It will take up to 120ns for the SRST to complete Revision 1.22 (09-25-08) Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface 0000h Size: 32 bits DESCRIPTION DATASHEET Datasheet TYPE DEFAULT 001000b 00000b R/W/SC SMSC LAN9420/LAN9420i...

  • Page 105: Transmit Poll Demand Register (Tx_Poll_Demand)

    - TU) is not asserted. A write to this register is only effective if the transmit process is in the suspended state. A Read of this register will timeout and invalid data will be returned. SMSC LAN9420/LAN9420i 0004h Size:...

  • Page 106: Receive Poll Demand Register (Rx_Poll_Demand)

    A Read of this register will timeout and invalid data will be returned. Revision 1.22 (09-25-08) Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface 0008h Size: 32 bits DESCRIPTION DATASHEET Datasheet TYPE DEFAULT SMSC LAN9420/LAN9420i...

  • Page 107: Receive List Base Address Register (Rx_Base_Addr)

    Host memory. Writing this register is only valid when the RX DMA engine is in the stopped state. When stopped, this register must be written before the START command is given. RESERVED SMSC LAN9420/LAN9420i 000Ch Size: 32 bits...

  • Page 108: Transmit List Base Address Register (Tx_Base_Addr)

    TX DMA engine is in the stopped state. When stopped, this register must be written before the START command is given. RESERVED Revision 1.22 (09-25-08) Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface 0010h Size: 32 bits DESCRIPTION DATASHEET Datasheet TYPE DEFAULT 28‘h0 SMSC LAN9420/LAN9420i...

  • Page 109: Dma Controller Status Register (Dmac_Status)

    This bit is the logical OR of other bits within this register. Only unmasked bits affect this register. Below is the list of bits: DMAC_STATUS[1]: Transmit process stopped (TPS) DMAC_STATUS[7]: Receive buffer unavailable (RU) DMAC_STATUS[8]: Receive process stopped (RPS) SMSC LAN9420/LAN9420i 0014h Size: 32 bits DESCRIPTION...
  • Page 110 Indicates that a frame transmission was completed and TDES1[31] is set in the first Descriptor indicating that the TX descriptor has been updated. Revision 1.22 (09-25-08) Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface DESCRIPTION DATASHEET Datasheet TYPE DEFAULT R/WC R/WC R/WC R/WC R/WC R/WC R/WC SMSC LAN9420/LAN9420i...

  • Page 111: Dma Controller Control (Operation Mode) Register (Dmac_Control)

    When set, this bit instructs the DMA Controller to process a second frame of transmit data even before status for the first frame is obtained. This bit affects the DMA Controller but not the MIL. SMSC LAN9420/LAN9420i 0018h Size: 32 bits...
  • Page 112 Receive Process State (RS) as Running and Receive Process Stopped (RPS) does not assert). RESERVED Revision 1.22 (09-25-08) Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface DESCRIPTION MAC Control Register (MAC_CR)). MAC Control Register DATASHEET Datasheet TYPE DEFAULT SMSC LAN9420/LAN9420i...

  • Page 113: Dma Controller Interrupt Enable Register (Dmac_Intr_Ena)

    Interrupt Summary Enable bit (bit [15]) are set. RESERVED RESERVED Transmit Buffer Unavailable (TU_EN) The Transmit Buffer Unavailable Interrupt is enabled only when this bit and the Normal Interrupt Summary Enable bit (bit [16]) are set. SMSC LAN9420/LAN9420i 001Ch Size: 32 bits DESCRIPTION DATASHEET...
  • Page 114 The Transmit Interrupt is enabled only when this bit and the Normal Interrupt Summary Enable bit (bit [16]) are set. Revision 1.22 (09-25-08) Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface DESCRIPTION DATASHEET Datasheet TYPE DEFAULT SMSC LAN9420/LAN9420i...

  • Page 115: Missed Frame And Buffer Overflow Counter Reg (Miss_Frame_Cntr)

    This field indicates the number of frames missed due to receive buffers being unavailable. This counter is incremented each time the DMAC discards an incoming frame. This counter is automatically cleared on a read. SMSC LAN9420/LAN9420i 0020h Size: 32 bits...

  • Page 116: Current Transmit Buffer Address Register (Tx_Buff_Addr)

    This field contains the pointer to the current buffer address pointer used by the DMAC during TX operation. Revision 1.22 (09-25-08) Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface 0050h Size: 32 bits DESCRIPTION DATASHEET Datasheet TYPE DEFAULT 32‘h0 SMSC LAN9420/LAN9420i...

  • Page 117: Current Receive Buffer Address Register (Rx_Buff_Addr)

    This register points to the current receive buffer address being read by the DMAC. BITS 31:0 RX_BUFF_ADDR This field contains the pointer to the current buffer address pointer used by the DMAC during RX operation. SMSC LAN9420/LAN9420i 0054h Size: 32 bits DESCRIPTION DATASHEET...

  • Page 118: Mac Control And Status Registers (Mcsr)

    MAC Address Low Multicast Hash Table High Multicast Hash Table Low MII Address MII Data Flow Control VLAN1 Tag VLAN2 Tag Wakeup Frame Filter Wakeup Control and Status Checksum Offload Engine Control Reserved for future use DATASHEET Datasheet REGISTER NAME SMSC LAN9420/LAN9420i...

  • Page 119: Mac Control Register (Mac_Cr)

    When set, the address check Function operates in Inverse filtering mode. This is valid only during Perfect filtering mode. Pass Bad Frames (PASSBAD) When set, all incoming frames that passed address filtering are received, including runt frames and collided frames. SMSC LAN9420/LAN9420i 0080h Size: 32 bits DESCRIPTION...
  • Page 120 RESERVED Hash/Perfect Filtering Mode (HPFILT) When reset (0), LAN9420/LAN9420i will implement a perfect address filter on incoming frames according the address specified in the MAC address register. When set (1), the address check function does imperfect address filtering of multicast incoming frames according to the hash table specified in the multicast hash table register.
  • Page 121 When set, the MAC’s transmitter is enabled and it will transmit frames from the buffer onto the cable. When reset, the MAC’s transmitter is disabled and will not transmit any frames. SMSC LAN9420/LAN9420i DESCRIPTION (Note 4.4) after it detects a collision, where:...
  • Page 122 (DMAC_STATUS will continue to show the Receive Process State (RS) as Running and Receive Process Stopped (RPS) does not assert). RESERVED Revision 1.22 (09-25-08) Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface DESCRIPTION prior to enabling the receiver (by setting DATASHEET Datasheet TYPE DEFAULT SMSC LAN9420/LAN9420i...

  • Page 123: Mac Address High Register (Addrh)

    6 octet of the RX frame. BITS 31:16 RESERVED 15-0 Physical Address [47:32] This field contains the upper 16 bits (47:32) of the physical address of the LAN9420/LAN9420i device. SMSC LAN9420/LAN9420i 0084h Size: 32 bits DESCRIPTION DATASHEET TYPE DEFAULT FFFFh Revision 1.22 (09-25-08)

  • Page 124: Mac Address Low Register (Addrl)

    Table 4.6 ADDRL, ADDRH Byte Ordering ORDER OF RECEPTION ON ETHERNET Figure 0xBC 0x9A ADDRH 0x78 0x56 0x34 0x12 ADDRL DATASHEET Datasheet 32 bits TYPE DEFAULT 32‘hF 4.2. The values required to automatically Section 3.3.5.1, "EEPROM Format," on SMSC LAN9420/LAN9420i...

  • Page 125: Multicast Hash Table High Register (Hashh)

    The Multicast Hash Table Hi register contains the higher 32 bits of the hash table and the Multicast Hash Table Low register contains the lower 32 bits of the hash table. BITS 31-0 Upper 32 bits of the 64-bit Hash Table SMSC LAN9420/LAN9420i 008Ch Size: 32 bits DESCRIPTION...

  • Page 126: Multicast Hash Table Low Register (Hashl)

    This register defines the lower 32-bits of the Multicast Hash Table. Please refer to Section 4.4.4, "Multicast Hash Table High Register (HASHH)," on page 125 for further details. BITS DESCRIPTION TYPE DEFAULT 31-0 Lower 32 bits of the 64-bit Hash Table 32‘h0 Revision 1.22 (09-25-08) SMSC LAN9420/LAN9420i DATASHEET...

  • Page 127: Mii Access Register (Mii_Access)

    The MII data register must be kept valid until the MAC clears this bit during a PHY write operation. The MII data register is invalid until the MAC has cleared this bit during a PHY read operation. SMSC LAN9420/LAN9420i 0094h Size:...

  • Page 128: Mii Data Register (Mii_Data)

    PHY before an MII write operation. Revision 1.22 (09-25-08) Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface 0098h Size: 32 bits DESCRIPTION DATASHEET Datasheet for further details. TYPE DEFAULT 0000h SMSC LAN9420/LAN9420i...

  • Page 129: Flow Control Register (Flow)

    1. During a transfer of control frame, this bit continues to be set, signifying that a frame transmission is in progress. After the PAUSE control frame’s transmission is complete, the MAC resets to 0. SMSC LAN9420/LAN9420i 009Ch Size:...

  • Page 130: Vlan1 Tag Register (Vlan1)

    13 and 14 frame detection. Revision 1.22 (09-25-08) Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface 00A0h Size: 32 bits DESCRIPTION bytes of the incoming frames for VLAN1 DATASHEET Datasheet TYPE DEFAULT FFFFh SMSC LAN9420/LAN9420i...

  • Page 131: Vlan2 Tag Register (Vlan2)

    VLAN2 Tag Identifier (VTI2) This contains the VLAN Tag field to identify the VLAN2 frames. This field is compared with the 13 and 14 frame detection. SMSC LAN9420/LAN9420i 00A4h Size: 32 bits DESCRIPTION bytes of the incoming frames for VLAN2...

  • Page 132: Wakeup Frame Filter (Wuff)

    WFF may cause the internal read/write pointers to be left in a position other than pointing to the first entry. Revision 1.22 (09-25-08) Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface 00A8h Size: 32 bits DESCRIPTION DATASHEET Datasheet TYPE DEFAULT 0000_0000h SMSC LAN9420/LAN9420i...

  • Page 133: Wakeup Control And Status Register (Wucsr)

    When set, remote wakeup mode is enabled and the MAC is capable of detecting wakeup frames as programmed in the Wakeup Frame Filter. Magic Packet Enable (MPEN) When set, Magic Packet wakeup mode is enabled. RESERVED SMSC LAN9420/LAN9420i 00ACh Size: 32 bits DESCRIPTION...

  • Page 134: Checksum Offload Engine Control Register (Coe_Cr)

    (PADSTR bit of the and vice versa. These functions cannot be enabled simultaneously. Revision 1.22 (09-25-08) Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface 00B0h Size: 32 bits DESCRIPTION MAC Control Register (MAC_CR)) DATASHEET Datasheet TYPE DEFAULT SMSC LAN9420/LAN9420i...

  • Page 135: Phy Registers

    Auto-Negotiation Link Partner Ability Register Auto-Negotiation Expansion Register Mode Control/Status Register Special Modes Control / Status Indication Register Interrupt Source Register Interrupt Mask Register PHY Special Control/Status Register SMSC LAN9420/LAN9420i Table 4.7, "PHY Control and Status Registers" REGISTER NAME DATASHEET below. Revision 1.22 (09-25-08)

  • Page 136: Basic Control Register

    = 1). Collision Test 1 = enable COL test, 0 = disable COL test RESERVED Revision 1.22 (09-25-08) Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Size: 16 bits DESCRIPTION DATASHEET Datasheet TYPE DEFAULT R/W/SC R/W/SC SMSC LAN9420/LAN9420i...

  • Page 137: Basic Status Register

    1 = link is up, 0 = link is down Jabber Detect 1 = jabber condition detected 0 = no jabber condition detected Extended Capabilities 1 = supports extended capabilities registers 0 = does not support extended capabilities registers. SMSC LAN9420/LAN9420i Size: 16 bits DESCRIPTION DATASHEET TYPE...

  • Page 138: Phy Identifier 1

    Datasheet 4.5.3 PHY Identifier 1 Index (In Decimal): Size: 16 bits BITS DESCRIPTION TYPE DEFAULT 15:0 PHY ID Number 0007h Assigned to the 3rd through 18th bits of the Organizationally Unique Identifier (OUI), respectively. Revision 1.22 (09-25-08) SMSC LAN9420/LAN9420i DATASHEET...

  • Page 139: Phy Identifier 2

    BITS 15:10 PHY ID Number b Assigned to the 19th through 24th bits of the OUI. Model Number Six-bit manufacturer’s model number. Revision Number Four-bit manufacturer’s revision number. SMSC LAN9420/LAN9420i Size: 16 bits DESCRIPTION DATASHEET TYPE DEFAULT C0C3h Revision 1.22 (09-25-08)

  • Page 140: Auto Negotiation Advertisement

    11), the device will only be configured to, at most, one of the two settings upon auto- negotiation completion. Revision 1.22 (09-25-08) Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Size: 16 bits DESCRIPTION 4.5) DATASHEET Datasheet TYPE DEFAULT 00001b SMSC LAN9420/LAN9420i...

  • Page 141: Auto Negotiation Link Partner Ability

    10BASE-T Full Duplex 1 = 10Mbps with full duplex 0 = no 10Mbps with full duplex ability 10BASE-T 1 = 10Mbps able, 0 = no 10Mbps ability Selector Field [00001] = IEEE 802.3 SMSC LAN9420/LAN9420i Size: 16 bits DESCRIPTION DATASHEET TYPE DEFAULT 00001b Revision 1.22 (09-25-08)

  • Page 142: Auto Negotiation Expansion

    1 = link partner has auto-negotiation ability 0 = link partner does not have auto-negotiation ability Revision 1.22 (09-25-08) Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Size: 16 bits DESCRIPTION DATASHEET Datasheet TYPE DEFAULT RO/LH RO/LH SMSC LAN9420/LAN9420i...

  • Page 143: Mode Control/Status

    RESERVED ENERGYON Indicates whether energy is detected. This bit goes to a “0” if no valid energy is detected within 256ms. Reset to “1” by hardware reset, unaffected by SW reset. RESERVED SMSC LAN9420/LAN9420i Size: 16 bits DESCRIPTION DATASHEET TYPE DEFAULT Revision 1.22 (09-25-08)

  • Page 144: Special Modes

    101b Repeater mode. Auto-negotiation enabled. 100BASE-TX Half Duplex is advertised. CRS is active during Receive. 110b RESERVED - Do not set LAN9420/LAN9420i in this mode. 111b All capable. Auto-negotiation enabled. Revision 1.22 (09-25-08) Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface...

  • Page 145: Special Control/Status Indications

    1 - Receive PLL 10M is locked on the reference clock. In this mode 10M data packets cannot be received. RESERVED XPOL Polarity state of the 10BASE-T: 0 – Normal polarity 1 – Reversed polarity RESERVED SMSC LAN9420/LAN9420i Size: 16 bits DESCRIPTION DATASHEET TYPE DEFAULT R/W, NASR Revision 1.22 (09-25-08)

  • Page 146: Interrupt Source Flag

    1= Auto-Negotiation Page Received, 0 = not source of interrupt RESERVED Revision 1.22 (09-25-08) Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Size: 16 bits DESCRIPTION DATASHEET Datasheet TYPE DEFAULT RO/LH RO/LH RO/LH RO/LH RO/LH RO/LH RO/LH SMSC LAN9420/LAN9420i...

  • Page 147: Interrupt Mask

    Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet 4.5.12 Interrupt Mask Index (In Decimal): BITS 15:8 RESERVED Mask Bits 1 = interrupt source is enabled, 0 = interrupt source is masked SMSC LAN9420/LAN9420i Size: 16 bits DESCRIPTION DATASHEET TYPE DEFAULT Revision 1.22 (09-25-08)

  • Page 148: Phy Special Control/Status

    Note 4.6 Bit 6 of this register must be set to ‘1’ for write operations. Revision 1.22 (09-25-08) Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Size: 16 bits DESCRIPTION DATASHEET Datasheet TYPE DEFAULT Note 4.6 000b SMSC LAN9420/LAN9420i...

  • Page 149: Pci Configuration Space Csr (Config Csr)

    REGISTER NAME 00h – 3Fh 40h – 74h RESERVED PCI_PMC PCI_PMCSR SMSC LAN9420/LAN9420i Section 3.7, "Power Management," on page 73 DESCRIPTION Standard PCI Header Registers (See for details). PCI Power Management Capabilities Register (PCI_PMC) PCI Power Management Control and Status Register...

  • Page 150: Table 4.10 Standard Pci Header Registers Supported

    FFFFFF01h after writing FFFFFFFFh. Note 4.9 The Subsystem Vendor ID and Subsystem Device ID can be configured by the serial EEPROM. if no EEPROM is connected to LAN9420/LAN9420i, then the default values in the table are used. Revision 1.22 (09-25-08)

  • Page 151: Pci Power Management Capabilities Register (Pci_Pmc)

    Definition as described in the PCI Bus Power Management Interface Specification Revision 1.1. BITS PME Support from D3 COLD When this bit is set, LAN9420/LAN9420i is capable asserting nPME from the state. When this bit is cleared, the device will not assert nPME from COLD the D3 state.
  • Page 152 Note 4.10 The default state of this field is dependant on the setting of the VAUXDET signal as noted in the description. Revision 1.22 (09-25-08) Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface DESCRIPTION DATASHEET Datasheet TYPE DEFAULT 010b SMSC LAN9420/LAN9420i...

  • Page 153: Pci Power Management Control And Status Register (Pci_Pmcsr)

    If PME_EN is cleared, the device will automatically place the PHY into General Power-Down when entering the D3 RESERVED SMSC LAN9420/LAN9420i Size: 32 bits DESCRIPTION bit in this register is set. When this bit is state.
  • Page 154 PCI bus; however D[1:0] are ignored and no state change occurs. Note 4.11 The default state of this field is dependant on the setting of the VAUXDET signal as noted in the description. Revision 1.22 (09-25-08) SMSC LAN9420/LAN9420i DATASHEET...

  • Page 155: Chapter 5 Operational Characteristics

    Supply Voltage (VDD33A, VDD33BIAS, VDD33IO) ......+3.3V +/- 300mV Ambient Operating Temperature in Still Air (T **Proper operation of LAN9420/LAN9420i is guaranteed only within the ranges specified in this section. SMSC LAN9420/LAN9420i (Note 5.1) .

  • Page 156: Power Consumption

    Power Consumption This section details the power consumption of LAN9420/LAN9420i as measured during various modes of operation. Power consumption values are provided for both the device-only, and for the device plus Ethernet components. Note: Power dissipation is determined by operating frequency, temperature, and supply voltage, as well as external source/sink requirements.

  • Page 157: D3 - Enabled For Wake Up Packet Detection

    Ambient Operating Temperature in Still Air (T 10BASE-T Full Duplex Supply current (VDD33IO, VDD33BIAS, VDD33A) Power Dissipation (Device Only) Power Dissipation (Device and Ethernet components) Ambient Operating Temperature in Still Air (T SMSC LAN9420/LAN9420i TYPICAL (@ 3.3V) TYPICAL (@ 3.3V) DATASHEET...

  • Page 158: D3 - Phy In General Power Down Mode

    Note: Power dissipation is determined by temperature, supply voltage, as well as external source/sink current requirements. Revision 1.22 (09-25-08) Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface TYPICAL (@ 3.3V) MAXIMUM (@ 3.6V) Note 5.5 Note 5.5 Section 5.2, "Operating Conditions**". DATASHEET Datasheet UNIT UNIT SMSC LAN9420/LAN9420i...

  • Page 159: Dc Specifications

    5V PCI system, or connected to 5V logic without appropriate voltage level translation. Note 5.8 This specification applies to all IPCI type inputs and tri-stated bi-directional PCI pins. Note 5.9 XI can optionally be driven from a 25MHz single-ended clock oscillator. SMSC LAN9420/LAN9420i Table 5.6 I/O Buffer Characteristics -0.3 1.01 1.18 1.35...

  • Page 160: Table 5.7 100Base-Tx Transceiver Characteristics

    Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface SYMBOL 1050 -950 -1050 SYMBOL DATASHEET Datasheet UNITS NOTES mVpk Note 5.10 mVpk Note 5.10 Note 5.10 Note 5.10 Note 5.10 Note 5.11 Note 5.12 UNITS NOTES Note 5.13 SMSC LAN9420/LAN9420i...

  • Page 161: Ac Specifications

    Datasheet AC Specifications This section contains timing information for non-PCI signals. Note: LAN9420/LAN9420i adheres to the PCI Local Bus Specification revision 3.0. Refer to the Conventional PCI 3.0 Specification for PCI timing details and parameters. 5.5.1 Equivalent Test Load (Non-PCI Signals) Output timing specifications assume the 25pF equivalent test load illustrated in Note: This test load is not applicable to PCI signals.

  • Page 162: Pci Clock Timing

    PCI Clock Timing The following specifies the PCI clock requirements for LAN9420/LAN9420i: 0.5*VDD33IO 0.4*VDD33IO 0.3*VDD33IO SYMBOL DESCRIPTION PCICLK cycle time PCICLK high time high PCICLK low time PCICLK slew rate (Note Note 5.14 This slew rate must be met across the minimum peak-to-peak portion of the clock waveform as shown in Revision 1.22 (09-25-08)

  • Page 163: Pci I/O Timing

    Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet PCI I/O Timing The following specifies the PCI I/O requirements for LAN9420/LAN9420i: PCICLK PCI OUTPUTS TRI-STATE PCI OUTPUTS PCI INPUTS Table 5.10 PCI I/O Timing Measurement Conditions SYMBOL test...

  • Page 164: Table 5.11 Pci I/O Timing Values

    Note 5.16 PCInRST is asserted and deasserted asynchronously with respect to the PCICLK signal. Revision 1.22 (09-25-08) Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Table 5.11 PCI I/O Timing Values (Note 5.15) (Note 5.15) (Note 5.16) DATASHEET Datasheet UNITS SMSC LAN9420/LAN9420i...

  • Page 165: Eeprom Timing

    Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet EEPROM Timing The following specifies the EEPROM timing requirements for LAN9420/LAN9420i: EECS cshckh EECLK EEDO EEDI EEDI (VERIFY) SYMBOL DESCRIPTION EECLK Cycle time ckcyc EECLK High time EECLK Low time...

  • Page 166: Clock Circuit

    Clock Circuit LAN9420/LAN9420i can accept either a 25MHz crystal (preferred) or a 25MHz single-ended clock oscillator (+/- 50ppm) input. If the single-ended clock oscillator method is implemented, XO should be left unconnected and XI should be driven with a nominal 0-3.3V clock signal. The input clock duty cycle is 40% minimum, 50% typical and 60% maximum.

  • Page 167: Chapter 6 Package Outline

    Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet Chapter 6 Package Outline 128-VTQFP Package Figure 6.1 LAN9420/LAN9420i 128-VTQFP Package Definition SMSC LAN9420/LAN9420i Revision 1.22 (09-25-08) DATASHEET...

  • Page 168: Figure 6.2 Lan9420/Lan9420I 128-Vtqfp Recommended Pcb Land Pattern

    E1 are maximum plastic body size dimensions including mold mismatch. 4. The pin 1 identifier may vary, but is always located within the zone indicated. Figure 6.2 LAN9420/LAN9420i 128-VTQFP Recommended PCB Land Pattern Revision 1.22 (09-25-08) Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface REMARKS 1.20...

  • Page 169: Chapter 7 Revision History

    Datasheet Chapter 7 Revision History REVISION LEVEL & DATE SECTION/FIGURE/ENTRY Rev. 1.22 (09-23-08) Rev. 1.21 Figure 1.2 LAN9420/LAN9420i Internal (07-30-08) Block Diagram on page 11 Figure 1.2 LAN9420/LAN9420i Internal Block Diagram on page 11 Section 4.5.5, "Auto Negotiation Advertisement," on page 140 Table 4.10, “Standard PCI...

This manual is also suitable for:

Lan9420i

Table of Contents