Sign In
Upload
Manuals
Brands
SMSC Manuals
Controller
LAN91C111
SMSC LAN91C111 Manuals
Manuals and User Guides for SMSC LAN91C111. We have
1
SMSC LAN91C111 manual available for free PDF download: Datasheet
SMSC LAN91C111 Datasheet (128 pages)
10/100 Non-PCI Ethernet Single Chip MAC + PHY
Brand:
SMSC
| Category:
Controller
| Size: 1 MB
Table of Contents
Product Features
1
Table of Contents
3
Chapter 1 General Description
8
Chapter 2 Pin Configurations
9
Figure 2.1 Pin Configuration - LAN91C111-FEAST 128 PIN TQFP
9
Figure 2.2 Pin Configuration - LAN91C111-FEAST 128 PIN QFP
10
Chapter 3 Block Diagrams
11
Figure 3.1 Basic Functional Block Diagram
11
Figure 3.2 Block Diagram
12
Figure 3.3 LAN91C111 Physical Layer to Internal MAC Block Diagram
13
Chapter 4 Signal Descriptions
14
Table 4.1 LAN91C111 Pin Requirements (128 Pin QFP and 1.0Mm TQFP Package)
14
Chapter 5 Description of Pin Functions
15
Chapter 6 Signal Description Parameters
19
Buffer Types
19
Chapter 7 Functional Description
20
Clock Generator Block
20
CSMA/CD Block
20
DMA Block
20
Arbiter Block
20
MMU Block
20
BIU Block
21
MAC-PHY Interface
21
Management Data Software Implementation
21
Management Data Timing
22
MI Serial Port Frame Structure
22
Figure 7.1 MI Serial Port Frame Timing Diagram
23
MII Packet Data Communication with External PHY
24
Figure 7.2 MII Frame Format & MII Nibble Order
24
Serial EEPROM Interface
25
Internal Physical Layer
25
Figure 7.3 TX/10BT Frame Format
26
Decoder
27
Encoder
27
MII Disable
27
Table 7.1 4B/5B Symbol Mapping
27
Clock and Data Recovery
29
Descrambler
29
Scrambler
29
Twisted Pair Transmitter
30
Figure 7.4 TP Output Voltage Template - 10 MBPS
31
Table 7.2 Transmit Level Adjust
32
Twisted Pair Receiver
33
Figure 7.5 TP Input Voltage Template -10MBPS
34
Collision
35
Start of Packet
35
End of Packet
36
Figure 7.6 SOI Output Voltage Template - 10MBPS
37
Link Integrity & Autonegotiation
37
Figure 7.7 Link Pulse Output Voltage Template - NLP, FLP
38
Figure 7.8 NLP VS. FLP Link Pulse
39
Jabber
40
Receive Polarity Correction
40
Full Duplex Mode
41
Loopback
41
PHY Interrupt
41
PHY Powerdown
41
Reset
42
Chapter 8 MAC Data Structures and Registers
43
Frame Format in Buffer Memory
43
Figure 8.1 Data Frame Format
43
Receive Frame Status
44
I/O Space
45
Bank Select Register
46
Table 8.1 Internal I/O Space Mapping
46
Bank 0 - Transmit Control Register
47
Bank 0 - EPH Status Register
48
Bank 0 - Receive Control Register
49
Bank 0 - Counter Register
50
Bank 0 - Memory Information Register
51
Bank 0 - Receive/Phy Control Register
51
Bank 1 - Configuration Register
54
Bank 1 - Base Address Register
55
Bank 1 - Individual Address Registers
55
Bank 1 - General Purpose Register
56
Bank 1 - Control Register
57
Bank 2 - MMU Command Register
58
Bank 2 - Packet Number Register
59
Bank 2 - FIFO Ports Register
60
Bank 2 - Pointer Register
61
Bank 2 - Data Register
62
Bank 2 - Interrupt Status Registers
62
Figure 8.2 Interrupt Structure
65
Bank 3 - Multicast Table Registers
66
Bank 3 - Management Interface
67
Bank 3 - Revision Register
67
Bank 3 - RCV Register
68
Bank 7 - External Registers
68
Chapter 9 PHY MII Registers
70
Table 9.1 MII Serial Frame Structure
71
Table 9.2 MII Serial Port Register MAP
73
Register 0. Control Register
74
Register 1. Status Register
75
Register 2&3. PHY Identifier Register
76
Register 4. Auto-Negotiation Advertisement Register
76
Register 5. Auto-Negotiation Remote End Capability Register
77
Register 16. Configuration 1- Structure and Bit Definition
78
Register 17. Configuration 2 - Structure and Bit Definition
79
Register 18. Status Output - Structure and Bit Definition
80
Register 19. Mask - Structure and Bit Definition
81
Register 20. Reserved - Structure and Bit Definition
82
Chapter 10 Software Driver and Hardware Sequence Flow
84
Software Driver and Hardware Sequence Flow for Power Management
84
Table 10.1 Typical Flow of Events for Placing Device in Low Power Mode
84
Typical Flow of Events for Transmit (Auto Release = 0)
85
Table 10.2 Flow of Events for Restoring Device in Normal Power Mode
85
Typical Flow of Events for Transmit (Auto Release = 1)
86
Typical Flow of Event for Receive
87
Figure 10.1 Interrupt Service Routine
88
Figure 10.2 RX INTR
89
Figure 10.3 TX INTR
90
Figure 10.4 TXEMPTY INTR (Assumes Auto Release Option Selected)
91
Figure 10.5 Drive Send and Allocate Routines
92
Figure 10.6 Interrupt Generation for Transmit, Receive, MMU
94
Chapter 11 Board Setup Information
95
Figure 11.1 64 X 16 Serial EEPROM Map
97
Chapter 12 Application Considerations
98
Table 12.1 VL Local Bus Signal Connections
98
Figure 12.1 LAN91C111 on VL BUS
100
Table 12.2 High-End ISA or Non-Burst EISA Machines Signal Connectors
100
Figure 12.2 LAN91C111 on ISA BUS
102
Table 12.3 EISA 32 Bit Slave Signal Connections
102
Figure 12.3 LAN91C111 on EISA BUS
104
Chapter 13 Operational Description
105
Maximum Guaranteed Ratings
105
DC Electrical Characteristics
105
Twisted Pair Characteristics, Transmit
108
Twisted Pair Characteristics, Receive
109
Chapter 14 Timing Diagrams
110
Figure 14.1 Asynchronous Cycle - Nads=0
110
Figure 14.2 Asynchronous Cycle - Using Nads
111
Figure 14.3 Asynchronous Cycle - Nads=0
112
Figure 14.4 Asynchronous Ready
112
Figure 14.5 Burst Write Cycles - Nvlbus=1
113
Figure 14.6 Burst Read Cycles - Nvlbus=1
114
Figure 14.7 Address Latching for All Modes
115
Figure 14.8 Synchronous Write Cycle - Nvlbus=0
115
Figure 14.9 Synchronous Read Cycle - Nvlbus=0
116
Figure 14.10MII Timing
117
Figure 14.11Transmit Timing
118
Table 14.1 Transmit Timing Characteristics
118
Figure 14.12Receive Timing, End of Packet - 10 MBPS
119
Table 14.2 Receive Timing Characteristics
119
Table 14.3 Collision and Jam Timing Characteristics
119
Figure 14.13Collision Timing, Receive
120
Figure 14.14Collision Timing, Transmit
121
Figure 14.15Jam Timing
122
Table 14.4 Link Pulse Timing Characteristics
123
Figure 14.16Link Pulse Timing
124
Figure 14.17FLP Link Pulse Timing
125
Chapter 15 Package Outlines
126
Figure 15.1 128 Pin TQFP Package Outline, 14X14X1.0 Body
126
Table 15.1 128 Pin TQFP Package Parameters
126
Figure 15.2 128 Pin QFP Package Outline, 3.9 MM Footprint
127
Table 15.2 128 Pin QFP Package Parameters
127
Chapter 16 Revision History
128
Table 16.1 Customer Revision History
128
Advertisement
Advertisement
Related Products
SMSC LAN9500
SMSC LAN9500i
SMSC LAN9420
SMSC LAN9420i
SMSC LAN9512
SMSC LAN9514
SMSC LAN9311i
SMSC LAN9311
SMSC LAN9303M
SMSC LAN9303
SMSC Categories
Motherboard
Controller
Switch
Network Hardware
Microcontrollers
More SMSC Manuals
Login
Sign In
OR
Sign in with Facebook
Sign in with Google
Upload manual
Upload from disk
Upload from URL