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The timing of input
read out on user's
computer
Input signal to
the input unit
Process of internal
circuit
Input read out data
on user's
computer
bit 0
bit 1: "Input change interruption" sets whether an interruption occurs or not when the input signal
changes. In case bit 1 is "1," an interruption occurs, and in case it is "0," an interruption does
not occur. If the input change interruption is effective, an interruption occurs when the input
signal of S-LINK V input address set as "1" at "13) HL00 + 00C0 to HL00 + 00FF, HL00 +
01C0 to HL00 + 01FF: input interrupting allowing address" changes.
bit 2: "Occurrence condition for input change interruption" sets whether the interruption occurs
ZLWK ³ 21
ON
Input signal of
input unit
OFF
1
bit 2
0
Interruption
Note: Occurrence condition for input change interruption is applied to all input interruptions.
(However, it cannot be selected in units of one channel.)
bit 3: "Error interruption" sets whether an interruption occurs or not when an error occurs.
When bit 3 is "1" an interruption occurs, and when bit 3 is "0" the interruption does not occur.
In case the error interruption is set to effective, the interruption occurs with OR operation
applied to all error occurrences.
For contents of error, check by "5) HL00 + 004A to B, HL00 + 014A to B: Error No. / Error state."
Error
Interruption
Note: In case bit 2 (Input change interruption) and bit 3 (Error interruption) are both "1," bit 3 (Error
interruption) has priority. Input change interruption does not occur.
13
Read out
ON
OFF
1
0
1
0
1
This cannot be read out because the timing of
the input signal and reading out do not match.
0
2))´ RU ³ 2))
Occurrence
In order to clear the interruption,
6) Command execution request register
7) Command completion response register
are used.
Error occurrence
Occurrence
In order to clear the interruption,
6) Command execution request register
7) Command completion response register
are used.
Read out
Read out
21´ ZKHQ ELW LV ³´
Hold
Occurrence
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