Siemens SIMATIC S7-400 Reference Manual
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Siemens SIMATIC S7-400 Reference Manual

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See also: Reference Manual , Function Manual
SIMATIC
Automation System S7-400
CPU Specifications
Reference Manual
This manual is part of the documentation
package with the order number
6ES7398-8AA03-8BA0
Edition 12/2002
A5E00165965-01
Preface, Contents
Structure of a CPU 41x
Memory Concept and
Startup Scenarios
Cycle and Reaction Times
of the S7-400
Technical Specifications
Index
1
2
3
4

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Summary of Contents for Siemens SIMATIC S7-400

  • Page 1 Preface, Contents Structure of a CPU 41x SIMATIC Memory Concept and Startup Scenarios Automation System S7-400 Cycle and Reaction Times of the S7-400 CPU Specifications Technical Specifications Reference Manual Index This manual is part of the documentation package with the order number 6ES7398-8AA03-8BA0 Edition 12/2002 A5E00165965-01...
  • Page 2 Trademarks SIMATIC, SIMATIC HMI and SIMATIC NET are registered trademarks of SIEMENS AG. Third parties using for their own purposes any other names in this document which refer to trademarks might infringe upon the rights of the trademark owners.

  • Page 3: Automation System S7

    Changes Since the Previous Version This manual describes S7 CPUs with firmware version 3.1. Certification The SIMATIC S7-400 product range has the following certificates: • Underwriters Laboratories, Inc.: UL 508 (Industrial Control Equipment) • Canadian Standards Association: CSA C22.2 Number 142, tested (Process Control Equipment) •...
  • Page 4 The SIMATIC S7-400 product range complies with the requirements of the AS/NZS 2064 standard (Australia and New Zealand). Standards The SIMATIC S7-400 product range complies with the requirements and criteria of the IEC 61131-2. Place of this Documentation in the Information Environment This manual is part of the documentation package for S7-400, M7-400.
  • Page 5 Preface Note In order to program and commission an S7-400 you require STEP 7 V52 as well as the following manuals or manual packages: Manual/ Chapter Overview Manual Package • Standard Software Installing and starting up STEP 7 on a programming device / PC •...
  • Page 6 Further Support If you have any technical questions, please get in touch with your Siemens representative or agent responsible. http://www.siemens.com/automation/partner...
  • Page 7 Technical Support Local time: 0:00 to 24:00 / 365 days Phone: +49 (0) 180 5050-222 Fax: +49 (0) 180 5050-223 E-Mail: adsupport@ siemens.com GMT: +1:00 Europe / Africa (Nuremberg) United States (Johnson City) Asia / Australia (Bejiing) Authorization Technical Support and...
  • Page 8 Service & Support in the Internet In addition to our documentation, we also offer you the benefit of all our knowledge on the Internet. http://www.siemens.com/automation/service&support There you will find: • A newsletter with all the latest information on your products •...

  • Page 9: Table Of Contents

    Contents Structure of a CPU 41x ..........Controls and Indicators of the CPUs .
  • Page 10 Contents Cycle and Reaction Times of the S7-400 ....... . . Cycle Time .
  • Page 11 Contents Figures Layout of the Controls and Indicators of the CPU 412-1 ....Layout of the Controls and Indicators of the CPU 41x-2 ....Layout of the Controls and Indicators of the CPU 41x-3 .
  • Page 12 Contents Tables LEDs of the CPUs ..........Positions of the Mode Selector .

  • Page 13: Structure Of A Cpu 41X

    Structure of a CPU 41x Chapter Overview In Section You Will Find On Page Controls and Indicators of the CPUs Monitoring Functions of the CPU Status and Error LEDs 1-11 Mode selector 1-14 Design and Function of Memory Cards 1-18 Multipoint Interface (MPI) 1-22 PROFIBUS DP interface...

  • Page 14: Controls And Indicators Of The Cpus

    Structure of a CPU 41x Controls and Indicators of the CPUs Controls and Indicators of the CPU 412-1 Module designation, version, abbre- viated order number and firmware CPU 412-1 version 6ES7412-1XF03-0AB0 LEDs INTF, EXTF, BUS1F, V3.0.0 FRCE, RUN, STOP BUS1F Slot for the memory card Mode selector Under cover...

  • Page 15: Layout Of The Controls And Indicators Of The Cpu 41X-2

    Structure of a CPU 41x Controls and Indicators of the CPU 41x-2 Module designation, version, abbre- viated order number and firmware version CPU 414-2 6ES7414-2XG03-0AB0 V3.0.0 LEDs INTF, EXTF, BUS1F, BUS2F, FRCE, RUN, STOP BUS1F BUS2F Slot for the memory card Mode selector Under cover MPI/PROFIBUS DP interface...

  • Page 16: Layout Of The Controls And Indicators Of The Cpu 41X-3

    Structure of a CPU 41x Controls and Indicators of the CPU 41x-3 Module designation, version, abbre- viated order number and firmware version CPU 416-3 6ES7416-3XL00-0AB0 V3.0.0 LEDs INTF, EXTF, BUS1F, LEDs BUS2F, FRCE, RUN, STOP IFM1F BUS1F BUS2F IFM1F Slot for the memory card Mode selector Under cover Under cover...

  • Page 17: Layout Of The Controls And Indicators Of The Cpu

    Structure of a CPU 41x Controls and Indicators of the CPU 417-4 Module designation, version, abbre- viated order number and firmware version LEDs INTF, EXTF, BUS1F, LEDs V3.0.0 BUS2F, FRCE, RUN, STOP IFM1F, IFM2F BUS1F BUS2F IFM1F IFM2F Slot for the memory card Mode selector Under cover Under cover...

  • Page 18: Leds Of The Cpus

    Structure of a CPU 41x Table 1-1 LEDs of the CPUs Color Meaning In CPU 412-1 412-2 414-3 417-4 414-2 416-3 416-2 INTF Internal fault EXTF External fault FRCE yellow Active force request green RUN mode STOP yellow STOP mode BUS1F Bus fault at MPI/PROFIBUS DP interface 1...
  • Page 19 Structure of a CPU 41x Slot for Interface Modules You can insert one interface module (IF module) for each CPUs 41x-3 and 41x-4 in this slot. Interface for Memory Expansion CPU 417-4 also features interfaces for memory expansion. These make it possible to expand the working memory.
  • Page 20 Structure of a CPU 41x Incoming Supply of External Backup Voltage at the “EXT.-BATT.” Socket You can use one or two backup batteries – depending on the module type – in the power supply modules of the S7-400 to do the following: •...

  • Page 21: Monitoring Functions Of The Cpu

    Structure of a CPU 41x Monitoring Functions of the CPU Monitoring and Error Messages The CPU hardware and the operating system have monitoring functions that ensure that the system functions correctly and that there is a defined response in the event of an error. A number of errors will also produce a response from the user program.
  • Page 22 Structure of a CPU 41x Type of Cause of Fault Response of the Operating Error LED Fault/Error System • Priority class Priority class is called, but the OB 85 call error corresponding OB is not available. If the OB is not loaded: The CPU INTF •...

  • Page 23: Status And Error Leds

    Structure of a CPU 41x Status and Error LEDs Status LEDs The two RUN and STOP LEDs on the front panel of a CPU informs you of the currently active CPU operating status. Meaning STOP CPU is in RUN state. CPU is in STOP state.
  • Page 24 Structure of a CPU 41x Error Displays and Points to Note, All CPUs The three LEDs INTF, EXTF and FRCE on the front panel of a CPU inform you about the errors and points to note during the execution of the user program. Meaning INTF EXTF...
  • Page 25 Structure of a CPU 41x Error LEDs and Points to Note, CPU 41x-3 and 41x-4 The CPUs 41x-3 and 41x-4 continue to have the LED IFM1F and LEDs IFM1F and IFM2F. These indicate errors in connection with the first and second module interfaces.

  • Page 26: Mode Selector

    Structure of a CPU 41x Mode Selector Function of the Mode Selector Using the mode selector, you can put the CPU in RUN/RUN-P or STOP mode or reset the memory of the CPU. STEP 7 offers further options for changing the mode.

  • Page 27: Positions Of The Mode Selector

    Structure of a CPU 41x Table 1-2 Positions of the Mode Selector Position Explanation RUN-P If there is no startup problem or error and the CPU can go into RUN, the CPU processes the user program or is idle. It is possible to access the I/O. The key cannot be removed in this position.

  • Page 28: Protection Levels Of A S7-400 Cpu

    Structure of a CPU 41x Table 1-3 Protection Levels of a S7-400 CPU Protection Function Switch Position Level • All programming device functions are permitted RUN-P/STOP (default setting). • It is permissible to load objects from the CPU into programming device. In other words, only read programming device functions are permitted.
  • Page 29 Structure of a CPU 41x Restart Following a restart, the user program resumes at the position at which it was interrupted. If the restart after power-on function (automatic restart) is to work, the S7-400 must have a battery backup. Reboot (Warm Restart) The user program is started again following a warm restart.

  • Page 30: Design And Function Of Memory Cards

    Structure of a CPU 41x Design and Function of Memory Cards Order Numbers The order numbers for memory cards are listed in the technical specifications in Chapter 4. Configuration The memory card is slightly larger than a credit card and protected by a strong metal casing.

  • Page 31: Types Of Memory Cards

    • Flash cards (FEPROM cards) Note Non-Siemens memory cards cannot be used in the S7-400. What Type of Memory Card Should You Use? Whether you use a RAM card or a Flash card depends on how you intend to use the memory card.

  • Page 32: Memory Requirements

    Structure of a CPU 41x RAM Card you use a RAM card, you must plug this into the CPU to load the user program. The user program is loaded with the help of the programming device (PG). You can load the entire user program or the individual parts such as FBs, FCs, OBs, DBs, or SDBs into the load memory in STOP mode or in RUN-P mode.
  • Page 33 Structure of a CPU 41x Changing the Memory Card To change the memory card, follow the steps outlined below: 1. Set the CPU to STOP. 2. Remove the plugged in memory card. Note If you remove the memory card, the CPU requests a memory reset by flashing the STOP indicator every three seconds.

  • Page 34: Multipoint Interface (Mpi)

    Structure of a CPU 41x Multipoint Interface (MPI) Connectable Devices You can, for example, connect the following nodes to the MPI: • Programming devices (PG/PC) • Operation and monitoring devices (OPs and TDs) • Additional SIMATIC S7 programmable controllers Some connectable devices take a supply of 24 V from the interface. This voltage is available there in non-isolated form.

  • Page 35: Profibus Dp Interface

    Structure of a CPU 41x Multipoint Interface as DP Interface You can also configure the MPI interface as a DP interface. To do this, you can reconfigure the MPI interface under STEP 7 in SIMATIC Manager. You can use this to set up a DP line with a maximum of 32 slaves. PROFIBUS DP Interface Connectable Devices You can connect any PROFIBUS DP slave that complies with the standard to the...

  • Page 36: Overview Of The Parameters For The S7-400 Cpus

    Structure of a CPU 41x Overview of the Parameters for the S7-400 CPUs Default Values All the parameters have default settings at delivery. These defaults, which are suitable for a whole range of standard applications, mean that the S7-400 can be used immediately without the need for further settings.
  • Page 37 Structure of a CPU 41x Parameter Assignment Tool You can set the individual CPU parameters using “Configuring Hardware” in STEP 7. Note If you make changes to the existing settings of the following parameters, the operating system carries out initializations like those during cold restart. •...

  • Page 38: Multicomputing

    Structure of a CPU 41x Multicomputing Chapter Overview Section Description Page 1.9.1 Peculiarities 1-28 1.9.2 Multicomputing Interrupt 1-29 1.9.3 Configuring and Programming Multicomputing Operation 1-29 What is Multicomputing Operation? Multicomputing operation is the operation of several (max. 4) multicomputing-capable central processing units at the same time in a central rack (central device) of the S7-400.

  • Page 39: Multicomputing Example

    Structure of a CPU 41x Example The figure below shows a programmable controller that is working in multicomputing mode. Each CPU can access the modules assigned to it (FM, CP, SM). CP, FM, CP, FM, CP, FM, CP, FM, CP, FM, CP, FM, CP, FM, CP, FM,...

  • Page 40: Peculiarities

    Structure of a CPU 41x 1.9.1 Peculiarities Slot Rules In multicomputing operation, up to four CPUs can be inserted at the same time in a central controller (CC) in any order. If you use CPUs that can only handle module start addresses that are divisible by 4 (usually CPUs before 10/98), you must keep to this rule for all the configured CPUs when you assign addresses! The rule applies should you also use CPUs that allow the bytewise assignment of module start addresses in single-computing...

  • Page 41: Multicomputing Interrupt

    Structure of a CPU 41x Interrupt Processing The following applies to interrupt processing: • Process interrupts and diagnostic interrupts are only sent to one CPU. • When a module fails or is removed or inserted, the interrupt is processed by the CPU that was assigned to the module at parameter assignment with STEP 7.

  • Page 42: Modifications To The System During Operation

    Modifications to the System During Operation Using CiR” You can download a free copy of this manual from the Internet address:http://www.siemens.com/automation/service&support You can modify the system during operation using CiR in system segments with distributed I/O. This requires a configuration as shown in the following illustration.
  • Page 43 Structure of a CPU 41x Hardware Requirements for Modification of a System During Operation The following hardware requirement must be fulfilled during the commissioning phase in order to be able to subsequently modify the system during operation: • An S7-400 standard CPU (CPU 412, CPU 414, CPU 416 or CPU 417), firmware V3.1 or later, or an S7-400-H-CPU (CPU 414-4H or CPU 417-4H) in single mode.
  • Page 44 Structure of a CPU 41x Software Requirements for System Modifications During Operation To be able to change a configuration in RUN mode, the user program must fulfill the following requirement: it must be written in such a way that station failures, module faults or exceeding cycle times does not make the CPU go to STOP.
  • Page 45 Structure of a CPU 41x Note If you wish to add or remove slaves or modules or make changes to an existing assignment to a process image partition, you can only do so on a maximum of four DP master systems. Any other changes during to the system operation that are not expressly listed above are not allowed and are not included in the this documentation.

  • Page 46: Cpu 41X As Dp Master/Dp Slave

    Structure of a CPU 41x 1.11 CPU 41x as DP Master/DP Slave Introduction This section contains the properties and technical specifications for the CPUs 412-1, 412-2, 414-2, 414-3, 416-2, 416-3 and 417-4 that you will require if you want to use the CPU as a DP master or as a DP slave and configure them for direct communication.

  • Page 47: Dp Address Areas Of The Cpus 41X

    Structure of a CPU 41x 1.11.1 DP Address Areas of the CPUs 41x Address Areas of the CPUs 41x Table 1-5 CPUs 41x (MPI/DP Interface as PROFIBUS DP) Address Area 412-1 412-2 414-2 416-2 MPI interface as PROFIBUS DP, inputs and 2048 2048 2048...

  • Page 48: Cpu 41X As Dp Master

    SIMATIC documentation we refer to this as DPV1. The new version features a few additions and simplifications. Some SIEMENS automation components already feature DPV1 functions. To be able to use these new features you first have to modify your system a bit. A detailed description of the conversion from EN 50170 to DPV1 is available as FAQ with the title “Changing from EN 50170 to DPV1”, FAQ contribution ID 7027576 at...
  • Page 49 DPV1.. You can you use DPV1 slaves even without the conversion to DPV1. The DPV1 slaves then behave like conventional slaves. DPV1 slaves from SIEMENS can be used in the S7-compatible mode. For DPV1 slaves from other manufacturers you need a GSD file to EN50170 earlier than Revision 3.
  • Page 50 Further Information You can find descriptions and information on changing from PROFIBUS DP to PROFIBUS DPV1 on the Internet at the following address: http://www.siemens.com/automation/service&support Under the item number 7027576 Monitor/Modify, Programming via PROFIBUS As an alternative to the MPI interface, you can use the PROFIBUS DP interface to program the CPU or execute the programming device functions Monitor and Modify.
  • Page 51 Structure of a CPU 41x SYNC/FREEZE With the SYNC control command, the DP slaves of the selected groups are switched to the Sync mode. In other words, the DP master transfers the current output data and instructs the DP slaves involved to freeze their outputs. With the following output frames, the DP slaves enter the output data in an internal buffer and the state of the outputs remains unchanged.

  • Page 52: Isochrone Updating Of The Process Image Partition

    Structure of a CPU 41x 1.11.3 Isochrone Updating of the Process Image Partition With SFC 126 “SYNC_PI“ you can update a process image partition of the inputs synchronous to the clock. A user program linked to a DP cycle can use this SFC to consistently and synchronously update input data located in a process image partition.

  • Page 53: Diagnostics Of The Cpu 41X As Dp Master

    Structure of a CPU 41x 1.11.4 Diagnostics of the CPU 41x as DP Master Diagnostics Using LEDs Table 1-7 explains the meaning of the BUSF LED. The BUSF LED assigned to the interface configured as the PROFIBUS DP interface will always light up or flash. Table 1-7 Meaning of the BUSF LED of the CPU 41x as DP Master BUSF...
  • Page 54 Structure of a CPU 41x Reading Out the Diagnosis with STEP 7 Table 1-8 Reading Out the Diagnosis with STEP 7 DP Master Block or Tab in Application Refer To... STEP 7 CPU 41x DP slave diagnostics To display the slave diagnosis See the section on hardware as plain text at the STEP 7 diagnostics in the STEP 7 online...

  • Page 55: Diagnostics With Cpu 41X

    Structure of a CPU 41x Evaluating the Diagnosis in the User Program The following figure shows you how to evaluate the diagnosis in the user program. CPU 41x Diagnostic event OB82 is called For the diagnosis of the relevant Read out OB82_MDL_ADDR components: Call SFB 54 (in the DPV1 environment) Read out OB82_IO_FLAG...

  • Page 56: Diagnostic Addresses For The Dp Master And Dp Slave

    Structure of a CPU 41x Diagnostic Addresses in Connection with DP Slave Functionality You assign diagnostic addresses for the PROFIBUS DP in the CPU 41x. Ensure during configuration that DP diagnostic addresses are assigned once to the DP master and once to the DP slave. S7 CPU as DP master S7 CPU as DP slave PROFIBUS...

  • Page 57: Event Detection Of The Cpus 41X As Dp Master

    Structure of a CPU 41x Event Detection Table 1-9 shows you how the CPU 41x as DP master detects any changes in the operating mode of a CPU as DP slave or interruptions in data transfer. Table 1-9 Event Detection of the CPUs 41x as DP Master Event What Happens in the DP Master •...

  • Page 58: Cpu 41X As Dp Slave

    STEP 7. If you require a description of the configuration and parameter assignment frame to carry out a check with a bus monitor, for example, you will find it on the Internet at http://www.ad.siemens.de/simatic-cs under the ID 1452338 Automation System S7-400 CPU Specifications...

  • Page 59: Intermediate Memory In The Cpu 41X As Dp Slave

    Structure of a CPU 41x Monitor/Modify, Programming via PROFIBUS As an alternative to the MPI interface, you can use the PROFIBUS DP interface to program the CPU or execute the programming device functions Monitor and Modify. To do this, you must enable these functions when you configure the CPU as DP slave in STEP 7.

  • Page 60: Configuration Example For The Address Areas

    Structure of a CPU 41x Address Areas of the Intermediate Memory Configure in STEP 7 the input and output address areas: • You can configure up to 32 input and output address areas. • Each of these address areas can be up to 32 bytes in size •...
  • Page 61 Structure of a CPU 41x Note You assign addresses for the intermediate memory from the DP address area of the CPU 41x. You must not reassign the addresses you have already assigned to the intermediate memory to the I/O modules on the CPU 41x. •...
  • Page 62 Structure of a CPU 41x Sample Program The small sample program below illustrates data transfer between the DP master and DP slave. This example contains the addresses from Table 1-10. In the DP Slave CPU In the DP Master CPU Preprocess data in the DP slave Transfer data to...

  • Page 63: Diagnostics Of The Cpu 41X As Dp Slave

    Structure of a CPU 41x 1.11.6 Diagnostics of the CPU 41x as DP Slave Diagnostics using LEDs – CPU 41x Table 1-11 explains the meaning of the BUSF LEDs. The BUSF LED assigned to the interface configured as the PROFIBUS DP interface will always light up or flash.

  • Page 64: Reading Out The Diagnostic Data With Step

    SFB 54 “RDREC” Applies to the DPV1 environment: To read out interrupt information within the associated interrupt OB FB 125/FC 125 To evaluate slave diagnosis The Internet page http://www.ad.siemens.de/ simatic-cs ID 387 257 Automation System S7-400 CPU Specifications 1-52 A5E00165965-01...
  • Page 65 Structure of a CPU 41x Table 1-12 Reading Out the Diagnostic Data with STEP 5 and STEP 7 in the Master System, Fortsetzung Automation System Block or Tab in Application Refer To... with DP Master STEP 7 FBs see the ET 200 SIMATIC S5 with FB 192 “IM308C”...

  • Page 66: Diagnostic Addresses For The Dp Master And Dp Slave

    Structure of a CPU 41x Diagnostic Addresses in Connection with DP Master Functionality You assign diagnostic addresses for the PROFIBUS DP in the CPU 41x. Ensure during configuration that DP diagnostic addresses are assigned once to the DP master and once to the DP slave. S7 CPU as DP master S7 CPU as DP slave PROFIBUS...

  • Page 67: Event Detection Of The Cpus 41X As Dp Slave

    Structure of a CPU 41x Event Detection Table 1-13 shows you how the CPU 41x as DP slave detects any operating mode changes or interruptions in data transfer. Table 1-13 Event Detection of the CPUs 41x as DP Slave Event What Happens in the DP Slave •...

  • Page 68: Structure Of The Slave Diagnosis

    Structure of a CPU 41x Structure of the Slave Diagnosis Byte 0 Byte 1 Station states 1 to 3 Byte 2 Byte 3 Master PROFIBUS Address High-Order Byte Byte 4 Manufacturer ID Byte 5 Low byte Byte 6 Module Diagnosis (The length depends on the Byte x number of configured address...

  • Page 69: Cpu 41X As Dp Slave: Station States 1 To 3

    Structure of a CPU 41x 1.11.7 CPU 41x as DP slave: Station States 1 to 3 Station states 1 to 3 Station status 1 to 3 provides an overview of the status of a DP slave. Table 1-15 Structure of the Station Status 1 (Byte 0) Meaning What to Do •...

  • Page 70: Structure Of Station Status 2 (Byte 1)

    Structure of a CPU 41x Table 1-16 Structure of Station Status 2 (Byte 1) Meaning 1: The DP slave must be assigned new parameters and reconfigured. 1: A diagnostic message has been issued. The DP slave cannot continue until the problem has been corrected (static diagnostic message).

  • Page 71: Structure Of The Manufacturer Id (Bytes 4, 5)

    Structure of a CPU 41x Manufacturer ID The manufacturer ID contains a code that describes the type of the DP slave. Table 1-19 Structure of the Manufacturer ID (Bytes 4, 5) Byte 4 Byte 5 Manufacturer ID for CPU 412-1 412-2 414-2 414-3...

  • Page 72: Structure Of The Module Diagnosis Of The Cpu 41X

    Structure of a CPU 41x Module Diagnosis The module diagnosis tells you for which of the configured address areas of the intermediate memory an entry has been made. Bit no. Byte 6 Length of the module diagnosis including byte 6 (depends on the number of configured address areas up to 6 bytes) Code for module diagnosis 7 6 5 4...

  • Page 73: Structure Of The Station Diagnosis

    Structure of a CPU 41x Station Diagnosis The station diagnosis provides detailed information on a DP slave. The station diagnosis starts as of byte x and can include up to 20 bytes. The figure below illustrates the structure and contents of the bytes for a configured address area of the intermediate memory.

  • Page 74: Bytes +4 To +7 For Diagnostic And Process Interrupts

    Structure of a CPU 41x As of byte x +4 The meaning of the bytes as of byte x+4 depends on byte x +1 (see Figure 1-15). In Byte x +1, the Code Stands for: Diagnostic Interrupt (01 Process Interrupt (02 The diagnostic data contain the 16 byte You can program 4 bytes of interrupt status information of the CPU.
  • Page 75 Structure of a CPU 41x Interrupts with the S7/M7 DP Master In the CPU 41x as a DP slave you can trigger a process interrupt in the DP master from the user program. You can trigger an OB 40 in the user program of the DP master by calling SFC 7 “DP_PRAL”.

  • Page 76: Direct Communication

    Structure of a CPU 41x 1.12 Direct Communication You can configure direct communication for PROFIBUS nodes as of STEP 7 V 5.x. The CPU 41x can participate in direct communication as the sender or recipient. “Direct Communication” represents a special type of communication relationship between PROFIBUS DP nodes.

  • Page 77: Direct Communication With Cpus 41X

    Structure of a CPU 41x Example Figure 1-17 uses an example to illustrate which direct communication “relationships” you can configure. All the DP masters and DP slaves in the figure are CPUs 41x. Note that other DP slaves (ET 200M, ET 200X, ET 200S) can only be senders.

  • Page 78: Diagnostics In Direct Communication

    Structure of a CPU 41x 1.12.2 Diagnostics in Direct Communication Diagnostic Addresses In direct communication you assign a diagnostic address in the recipient: S7-CPU as sender S7-CPU as recipient PROFIBUS Diagnostic address During configuration you specify a diagnostic address in the recipient that is assigned to the sender.

  • Page 79: Evaluation Of The Station Failure In The

    Structure of a CPU 41x Evaluation in the User Program The following table 1-21 shows you, for example, how you can evaluate a sender station failure in the recipient (see also Table 1-20). Table 1-21 Evaluation of the Station Failure in the Sender During Direct Communication In the Sender In the Recipient Diagnostic addresses: (example)

  • Page 80: Consistent Data

    Structure of a CPU 41x 1.13 Consistent Data Data that belongs together in terms of its content and a process state written at a specific point in time is known as consistent data. To maintain consistency, the data should not be changed or updated during processing or transmission. Example To ensure that the CPU has a consistent image of the process signals for the duration of cyclic program scanning, the process signals are read from the process...

  • Page 81: Consistency For Communication Blocks And Functions

    Structure of a CPU 41x 1.13.1 Consistency for Communication Blocks and Functions Using S7-400 the communication data is not processed in the scan cycle checkpoint; instead, this data is processed in fixed time slices during the program cycle. In the system the byte, word and double word data formats can always be processed consistently, in other words, the transfer or processing of 1 byte, 1 word (= 2 bytes) or 1 double word (= 4 bytes) cannot be interrupted.

  • Page 82: Writing Data Consistently To A Dp Standard Slave Using Sfc 15 "Dpwr_Dat"

    Structure of a CPU 41x 1.13.4 Writing Data Consistently to a DP Standard Slave Using SFC 15 “DPWR_DAT” Using SFC 15 “DPWR_DAT” (write consistent data to a DP standard slave) you can consistently write data to the DP standard slave addressed in the RECORD. The source range must have the same length as the one you have configured for the selected module with STEP 7.

  • Page 83: Consistent Data Access Without The Use Of Sfc 14 Or Sfc 15

    Structure of a CPU 41x 1.13.5 Consistent Data Access without the Use of SFC 14 or SFC 15 Consistent data access of > 4 bytes without using SFC 14 or SFC 15 is possible for the CPUs listed below. The data area of a DP slave that should transfer consistently is transferred to a process image partition.
  • Page 84 Structure of a CPU 41x Example: The following example (of the process image partition 3 “TPA 3”) shows such a configuration in HW Config: • TPA 3 at output: These 50 bytes are stored consistent in the process image partition 3 (pull-down list “Consistent over –> entire length”) and can therefore be read through the normal “load input xy”...

  • Page 85: Memory Concept And Startup Scenarios

    Memory Concept and Startup Scenarios Chapter Overview In Section Description On Page Overview of the Memory Concept of S7-400 CPUs Overview of the Startup Scenarios for S7-400-CPUs Automation System S7-400 CPU Specifications A5E00165965-01...

  • Page 86: Overview Of The Memory Concept Of S7-400 Cpus

    Memory Concept and Startup Scenarios Overview of the Memory Concept of S7-400 CPUs Subdivision of the Memory Areas You can divide the memory of the S7 CPUs into the following areas: External load memory RAM with battery backup or retentive flash Load memory memory For project data (blocks,...
  • Page 87 Memory Concept and Startup Scenarios Important Note for CPUs with Configurable Division of the Working Memory If you use parameter assignment to change the division of the working memory, the working memory is reorganized when the system data are downloaded to the CPU.
  • Page 88 Memory Concept and Startup Scenarios Memory Types in S7-400 CPUs • Load memory for project data, such as blocks, configuration and parameter assignment data, including symbols and comments as of version 5.1. • Working memory for the runtime-relevant blocks (code blocks and data blocks). •...

  • Page 89: Overview Of The Startup Scenarios For S7-400-Cpus

    Memory Concept and Startup Scenarios Overview of the Startup Scenarios for S7-400-CPUs Cold Restart • At a cold restart, all the data (process image, memory markers, timers, counters and data blocks) are reset to the start values stored in the program (load memory) - irrespective of whether they were configured as retentive or non-retentive.
  • Page 90 Memory Concept and Startup Scenarios Automation System S7-400 CPU Specifications A5E00165965-01...

  • Page 91: Cycle And Reaction Times Of The S7-400

    Cycle and Reaction Times of the S7-400 This chapter explains the composition of the cycle and reaction times of the S7-400. You can display the cycle time of your user program on the relevant CPU using the programming device (see manual Configuring Hardware and Communication Connections with STEP 7 Version 5.0 or higher).

  • Page 92: Cycle Time

    Cycle and Reaction Times of the S7-400 Cycle Time In this chapter you will learn about the composition of the cycle time and how you can calculate the cycle time. Definition of the Cycle Time The cycle time is the time which the operating system needs to process a program run –...

  • Page 93: Parts And Composition Of The Cycle Time

    Cycle and Reaction Times of the S7-400 The Cyclic Program Scanning Process The following table and figure illustrate the phases of cyclic program scanning. Table 3-1 Cyclic Program Scanning Step Process The operating system starts the scan cycle monitoring time. The CPU writes the values from the process-image output table in the output modules.

  • Page 94: Cycle Time Calculation

    Cycle and Reaction Times of the S7-400 Cycle Time Calculation Increasing the Cycle Time Basically, you should note that the cycle time of a user program is increased by the following: • Time-driven interrupt processing • Hardware interrupt processing (see also Section 3.8) •...

  • Page 95: Portions Of The Process Image Transfer Time

    Cycle and Reaction Times of the S7-400 Process Image Updating The table below shows the CPU times for process image updating (process image transfer time). The times listed in the table are “ideal values” that may be increased by the occurrence of interrupts and by CPU communications. The transfer time for process image updating is calculated as follows + portion in central rack (from line A of the following table) + portion in expansion rack with local connection (from line B)

  • Page 96: Portions Of The Process Image Transfer Time, H Cpus

    Cycle and Reaction Times of the S7-400 Table 3-4 Portions of the process image transfer time, H CPUs Portions CPU 41x-4H CPU 41x-4H n = number of bytes in the process image single mode redundant m= number of accesses to the process image c= number of consistency areas in the process image 20 ms 20 ms...

  • Page 97: User Program Processing Time For The Cpu 41X-4H

    Cycle and Reaction Times of the S7-400 Increasing the Cycle Time of the CPU 41x-4H With the CPU 41x-4H, you must further multiply the calculated cycle time by a factor specific to the CPU in question. This factor is shown in the table below: Table 3-5 User program processing time for the CPU 41x-4H Process...

  • Page 98: Different Cycle Times

    Cycle and Reaction Times of the S7-400 Different Cycle Times The length of the cycle time (T ) is not identical in each cycle. The following figure shows different cycle times, T and T is longer than T cyc1 cyc2 cyc2 cyc1 because the cyclically scanned OB 1 is interrupted by a time-of-day interrupt OB...

  • Page 99: Minimum Cycle Time

    Cycle and Reaction Times of the S7-400 Minimum Cycle Time You can set a minimum cycle time for a CPU in STEP 7. This is practical if • you want the intervals of time between the start of program scanning of OB1 (free cycle) to be roughly of the same length, or •...

  • Page 100: Communication Load

    Cycle and Reaction Times of the S7-400 Communication Load The CPU operating system continually makes available to communications the percentage you configured for the overall CPU processing performance (time sharing). If this processing performance is not required for communications, it is available for other processing tasks.
  • Page 101 Cycle and Reaction Times of the S7-400 Example: 20 % Communication Load You have configured a communication load of 20% in the hardware configuration. The calculated cycle time is 10 ms. A 20% communication load means that, on average, 200 ms and 800 ms of the time slice remain for communications and the user program, respectively.

  • Page 102: Dependency Of The Cycle Time On The Communication Load

    Cycle and Reaction Times of the S7-400 Dependency of the Actual Cycle Time on the Communication Load The following figure describes the non-linear dependency of the actual cycle time on the communication load. As an example, we have chosen a cycle time of 10 ms.

  • Page 103: Reaction Time

    Cycle and Reaction Times of the S7-400 Reaction Time Definition of the Reaction Time The reaction time is the time from an input signal being detected to changing an output signal linked to it. Variation The actual reaction time is somewhere between a shortest and a longest reaction time.

  • Page 104: Dp Cycle Times On The Profibus-Dp Network

    Cycle and Reaction Times of the S7-400 DP Cycle Times on the PROFIBUS-DP Network If you have configured your PROFIBUS-DP network with STEP 7, then STEP 7 will calculate the typical DP cycle time that must be expected. You can then have the DP cycle time of your configuration displayed for the bus parameters on the programming device.

  • Page 105: Shortest Reaction Time

    Cycle and Reaction Times of the S7-400 Shortest Reaction Time The following figure illustrates the conditions under which the shortest reaction time is achieved. SCC (OS) Delay of the inputs Immediately before the PII is read in, the status of the input under review changes.
  • Page 106 Cycle and Reaction Times of the S7-400 Longest Reaction Time The following figure shows you how the longest reaction time results. SCC (OS) Delay in the inputs + DP cycle time on the PROFIBUS-DP While the PII is being read in, the status of the input under review changes.

  • Page 107: Reducing The Reaction Time

    Cycle and Reaction Times of the S7-400 I/O Direct Accesses You can achieve faster reaction times by direct access to the I/O in the user program, for example with • L • T you can avoid the reaction times in part, as described above. Reducing the Reaction Time In this way the maximum reaction time is reduced to •...

  • Page 108: How Cycle And Reaction Times Are Calculated

    Cycle and Reaction Times of the S7-400 How Cycle and Reaction Times Are Calculated Cycle time 1. Using the Instruction List, determine the runtime of the user program. 2. Calculate and add the transfer time for the process image. You will find guide values for this in Table 3-3.

  • Page 109: Examples Of Calculating The Cycle Time And Reaction Time

    Cycle and Reaction Times of the S7-400 Examples of Calculating the Cycle Time and Reaction Time Example I You have installed an S7-400 with the following modules in the central rack: • One CPU 414-2 • Two digital input modules SM 421; DI 32×DC 24 V (4 byte each in PA) •...
  • Page 110 Cycle and Reaction Times of the S7-400 Calculation of the Longest Reaction Time • Longest reaction time 19.03 ms * 2 = 38.06 ms. • The delay in the inputs and outputs is negligible. • All the components are plugged into the central rack; DP cycle times do not therefore have to be taken into account.
  • Page 111 Cycle and Reaction Times of the S7-400 Calculation of the Actual Cycle Time • Allowance of communication load: 10.23 ms * 100 / (100-40) = 17.05 ms. • A time-of-day interrupt having a runtime of 0.5 ms is triggered every 100 ms. The interrupt cannot be triggered more than once during a cycle: 0.5 ms + 0.35 ms (in Table 3-7) = 0.85 ms.

  • Page 112: Interrupt Reaction Time

    Cycle and Reaction Times of the S7-400 Interrupt Reaction Time Definition of the Interrupt Reaction Time The interrupt reaction time is the time from when an interrupt signal first occurs to calling the first instruction in the interrupt OB. The following general rule applies: Interrupts having a higher priority take precedence.
  • Page 113 Cycle and Reaction Times of the S7-400 Increasing the Maximum Interrupt Reaction Time with Communication The maximum interrupt reaction time increases when communication functions are active. The increase is calculated with the following formula: tv = 200 ms + 1000 ms × n% CPU 412: tv = 100 ms + 1000 ms ×...

  • Page 114: Example Of Calculating The Interrupt Reaction Time

    Cycle and Reaction Times of the S7-400 Example of Calculating the Interrupt Reaction Time Parts of the Interrupt Reaction Time As a reminder, the hardware interrupt reaction time is made up of the following: • Hardware interrupt reaction time of the CPU •...

  • Page 115: Reproducibility Of Time-Delay And Watchdog Interrupts Of The Cpus

    Cycle and Reaction Times of the S7-400 3.10 Reproducibility of Time-Delay and Watchdog Interrupts Definition of “Reproducibility” Time-delay interrupt: The deviation with time from the first instruction of the interrupt OB being called to the programmed interrupt time. Watchdog interrupt The variation in the time interval between two successive calls, measures between the first instruction of the interrupt OB in each case.
  • Page 116 Cycle and Reaction Times of the S7-400 Automation System S7-400 CPU Specifications 3-26 A5E00165965-01...

  • Page 117: Technical Specifications

    Technical Specifications Chapter overview In Section You Will Find On Page Technical Specifications of the CPU 412-1; (6ES7412-1XF03-0AB0) Technical Specifications of the CPU 412-2; (6ES7412-2XG00-0AB0) Technical Specifications of the CPU 414-2; 4-10 (6ES7414-2XG03-0AB0) Technical Specifications of the CPU 414-3; 4-14 (6ES7414-3XJ00-0AB0) Technical Specifications of the CPU 416-2;...

  • Page 118: Technical Specifications Of The Cpu 412-1; (6Es7412-1Xf03-0Ab0)

    Technical Specifications Technical Specifications of the CPU 412-1; (6ES7412-1XF03-0AB0) CPU and Version Data Areas and Their Retentivity MLFB 6ES7412-1XF03-0AB0 Total retentive data areas Total working and load • (including memory bits; memory (with backup Firmware version V 3.1 times; counts) battery) Associated programming As of STEP7 V 5.2...
  • Page 119 Technical Specifications Configuration S7 Message Functions Central racks/expansion Max. 1/21 Number of stations that can Max. 8 units log on for message functions (e.g. WIN CC or Multicomputing Max. 4 CPUs SIMATIC OP) (with UR1 or UR2) Symbol-related messages Number of plug-in IMs Max.
  • Page 120 Physical RS 485/Profibus Yes, if the interface is active – Routing Isolated • DDB (GSD) file http://www.ad.siemens.de/c Power supply to interface Max. 150 mA si_e/gsd (15 VDC to 30 VDC) • Transmission rate Up to 12 Mbps Number of connection MPI: 16 •...
  • Page 121 Technical Specifications Programming Dimensions Programming language LAD, FBD, STL, SCL Mounting dimensions 25×290×219 W×H×D (mm) Instruction set See instruction list Slots required Bracket levels Weight Approx. 0.72 kg System functions (SFC) See instruction list Voltages, Currents Number of SFCs active at the same time Current consumption from Typ.

  • Page 122: Technical Specifications Of The Cpu 412-2; (6Es7412-2Xg00-0Ab0)

    Technical Specifications Technical Specifications of the CPU 412-2; (6ES7412-2XG00-0AB0) CPU and Version Data Areas and Their Retentivity MLFB 6ES7412-2XG00-0AB0 Total retentive data areas Total working and load • (including memory bits; memory (with backup Firmware version V 3.1 times; counts) battery) Associated programming As of STEP7 V 5.2...
  • Page 123 Technical Specifications Configuration S7 Message Functions Central racks/expansion Max. 1/21 Number of stations that can Max. 8 units log on for message functions (e.g. WIN CC or Multicomputing Max. 4 CPUs SIMATIC OP) (with UR1 or UR2) Symbol-related messages Number of plug-in IMs Max.
  • Page 124 Type of interface Integrated Yes, if the interface is active – Routing Physical RS 485/Profibus • DDB (GSD) file http://www.ad.siemens.de/c Isolated si_e/gsd Power supply to interface Max. 150 mA • Transmission rate Up to 12 Mbps (15 VDC to 30 VDC) •...
  • Page 125 Technical Specifications 2nd Interface System function blocks See instruction list (SFB) Type of interface Integrated Number of SFBs active at Physical RS 485/Profibus the same time Isolated • RD_REC Power supply to interface Max. 150 mA • WR_REC (15 VDC to 30 VDC) User program protection Password protection Number of connection...

  • Page 126: Technical Specifications Of The Cpu 414-2; (6Es7414-2Xg03-0Ab0)

    Technical Specifications Technical Specifications of the CPU 414-2; (6ES7414-2XG03-0AB0) CPU and Version Data Areas and Their Retentivity MLFB 6ES7414-2XG03-0AB0 Total retentive data areas Total working and load • (including memory bits; memory (with backup Firmware version V 3.1 times; counts) battery) Associated programming As of STEP7 V 5.2...
  • Page 127 Technical Specifications Configuration S7 Message Functions Central racks/expansion Max. 1/21 Number of stations that can Max. 8 units log on for message functions (e.g. WIN CC or Multicomputing Max. 4 CPUs SIMATIC OP) (with UR1 or UR2) Symbol-related messages Number of plug-in IMs Max.
  • Page 128 Yes, if the interface is active Physical RS 485/Profibus Yes, if the interface is active – Routing • Isolated DDB (GSD) file http://www.ad.siemens.de/c Power supply to interface Max. 150 mA si_e/gsd • (15 VDC to 30 VDC) Transmission rate Up to 12 Mbps •...
  • Page 129 Technical Specifications • 2nd Interface DPNRM_DG • Type of interface Integrated RDSYSST 1 to 8 • Physical RS 485/Profibus DP_TOPOL Isolated System function blocks See instruction list (SFB) Power supply to interface Max. 150 mA (15 VDC to 30 VDC) Number of SFBs active at the same time Number of connection...

  • Page 130: Technical Specifications Of The Cpu 414-3; (6Es7414-3Xj00-0Ab0)

    Technical Specifications Technical Specifications of the CPU 414-3; (6ES7414-3XJ00-0AB0) CPU and Version Data Areas and Their Retentivity MLFB 6ES7414-3XJ00-0AB0 Total retentive data areas Total working and load • (including memory bits; memory (with backup Firmware version V 3.1 times; counts) battery) Associated programming As of STEP7 V 5.2...
  • Page 131 Technical Specifications Configuration S7 Message Functions Central racks/expansion Max. 1/21 Number of stations that can Max. 8 units log on for message functions (e.g. WIN CC or Multicomputing Max. 4 CPUs SIMATIC OP) (with UR1 or UR2) Symbol-related messages Number of plug-in IMs Max.
  • Page 132 Max. 64 Kbytes Yes, if the interface is active – Routing • – Of which consistent 1 variable (462 bytes) DDB (GSD) file http://www.ad.siemens.de/c si_e/gsd S5-compatible Yes (via CP – max. 10 – • communication and FC AG_SEND and FC Transmission rate Up to 12 Mbps •...
  • Page 133 Technical Specifications Functionality System function blocks See instruction list • (SFB) PROFIBUS DP DP master/DP slave Number of SFBs active at DP Master the same time • Utilities • RD_REC – Programming • WR_REC device/OP communication User program protection Password protection –...

  • Page 134: Technical Specifications Of The Cpu 416-2; (6Es7416-2Xk02-0Ab0, 6Es7416-2Fk02-0Ab0)

    Technical Specifications Technical Specifications of the CPU 416-2; (6ES7416-2XK02-0AB0, 6ES7416-2FK02-0AB0) CPU and Version Data Areas and Their Retentivity MLFB 6ES7416-2XK02-0AB0 Total retentive data areas Total working and load • (including memory bits; memory (with backup Firmware version V 3.1 times; counts) battery) Associated programming As of STEP7 V 5.2...
  • Page 135 Technical Specifications Configuration S7 Message Functions Central racks/expansion Max. 1/21 Number of stations that can Max. 12 units log on for message functions (e.g. WIN CC or Multicomputing Max. 4 CPUs SIMATIC OP) (with UR1 or UR2) Symbol-related messages Number of plug-in IMs Max.
  • Page 136 Type of interface Integrated – Routing Yes, if the interface is active • Physical RS 485/Profibus DDB (GSD) file http://www.ad.siemens.de/c si_e/gsd Isolated • Transmission rate Up to 12 Mbps Power supply to interface Max. 150 mA • (15 VDC to 30 VDC)
  • Page 137 Technical Specifications • 2nd Interface DPNRM_DG • Type of interface Integrated RDSYSST 1 to 8 • Physical RS 485/Profibus DP_TOPOL Isolated System function blocks See instruction list (SFB) Power supply to interface Max. 150 mA (15 VDC to 30 VDC) Number of SFBs active at the same time Number of connection...

  • Page 138: Technical Specifications Of The Cpu 416-3; (6Es7416-3Xl00-0Ab0)

    Technical Specifications Technical Specifications of the CPU 416-3; (6ES7416-3XL00-0AB0) CPU and Version Data Areas and Their Retentivity MLFB 6ES7416-3XL00-0AB0 Total retentive data area Total working and load • (incl. memory markers, memory (with backup Firmware version V 3.1 timers, counters) battery) Associated programming As of STEP7 V 5.2...
  • Page 139 Technical Specifications Configuration S7 Message Functions Central racks/expansion Max. 1/21 Number of stations that can Max. 12 units log on for message functions (e.g. WIN CC or Multicomputing Max. 4 CPUs SIMATIC OP) (with UR1 or UR2) Symbol-related messages Number of plug-in IMs Max.
  • Page 140 Of which consistent 1 variable (462 bytes) – Routing Yes, if the interface is active • S5-compatible Yes (via CP – max. 10 – DDB (GSD) file http://www.ad.siemens.de/c communication and FC AG_SEND and si_e/gsd • AG_RECV) Transmission rate Up to 12 Mbps •...
  • Page 141 Technical Specifications • Number of DP slaves Max. 125 System function blocks See instruction list • (SFB) Address area Max. 8 Kbytes inputs/ 8 Kbytes outputs Number of SFBs active at • the same time User data per DP slave In accordance with the DP •...

  • Page 142: Technical Specifications Of The Cpu 417-4; (6Es7417-4Xl00-0Ab0)

    Technical Specifications Technical Specifications of the CPU 417-4; (6ES7417-4XL00-0AB0) • CPU and Version Size Max. 64 Kbytes MLFB 6ES7417-4XL00-0AB0 Local data (can be set) Max. 64 Kbytes • • Firmware version V 3.1 Preset 32 Kbytes Associated programming As of STEP7 V 5.2 Blocks package See instruction list...
  • Page 143 Technical Specifications Configuration S7 Message Functions Central racks/expansion Max. 1/21 Number of stations that can Max. 16 units log on for message functions (e.g. WIN CC or Multicomputing Max. 4 CPUs SIMATIC OP) (with UR1 or UR2) Symbol-related messages Number of plug-in IMs Max.
  • Page 144 Yes, if the interface is active – Routing • • User data per job Max. 64 Kbytes DDB (GSD) file http://www.ad.siemens.de/c – Of which consistent 1 variable (462 bytes) si_e/gsd • S5-compatible Yes (via CP – max. 10 – Transmission rate Up to 12 Mbps •...
  • Page 145 Technical Specifications • • Address area Max. 8 Kbytes inputs/ 8 DPNRM_DG • Kbytes outputs RDSYSST 1 to 8 • • User data per DP slave In accordance with the DP DP_TOPOL slave, but a maximum of System function blocks See instruction list 128 bytes of (SFB)

  • Page 146: Technical Specifications Of The Memory Cards

    Technical Specifications Technical Specifications of the Memory Cards Name Order Number Current BackupCurre Can Be Consumption Used in at 5 V M7-400 Typ. 0.5 mA MC 952 / 64 Kbytes / RAM 6ES7952-0AF00-0AA0 Typ. 20 mA – Max. 20 mA Max.
  • Page 147 3-4 Cycle load, communications via MPI and Configuration frame. see on the Internet at communication bus, 3-4 http://www.ad.siemens.de/simatic-cs Cycle Time, increasing, 3-4 Consistent data, 1-68 Cycle time, 3-2 Access to the working memory, 1-69 calculation example, 3-19...
  • Page 148 1-12 Memory Cards, 4-30 Flash card, 1-19 Parameter assignment frame. see on the Internet at http://www.ad.siemens.de/simatic-cs Parameters, 1-24 Process image updating, processing time, 3-4, Hardware interrupt processing, 3-23 Hardware interrupt reaction time, 3-22 Process interrupt, CPU 31x-2 as DP slave,...
  • Page 149 Index Reboot, 1-17 operating sequence, 1-17 Technical specifications Restart, 1-17 CPU 412-1, 4-2 operating sequence, 1-17 CPU 412-2, 4-6 CPU 414-2, 4-10 CPU 414-3, 4-14 CPU 416-2, 4-18 Scan cycle control, scan time, 3-7 CPU 416-3, 4-22 Scan time CPU 417-4, 4-26 operating system, 3-7 CPUs, 4-1 scan cycle control, 3-7...

  • Page 150: Index

    Index Automation System S7-400 CPU Specifications Index-4 A5E00165965-01...

Table of Contents