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Hardware Integration Guide
Table 63.
SPI Master Timing Characteristics
Parameter
SPI clock frequency
T
t(ch)
t(cl)
t(mov)
t(mis)
t(moh)
t(tse)
t(tsd)
6.16.4. SPI Pin Description
Refer to the following table for the SPI interface pin description.
Table 64.
SPI Pin Description
Signal
Pin #
SPI-CLK
CE4
SPI-MISO
CE3
SPI-MOSI
CD4
SPI_CS
CD5
6.16.5. Application
A 4-wire SPI configuration has the input and output data lines disassociated.
Figure 26.
Example of 4-wire SPI Bus Application
4116922
SPI clock period
Clock high
Clock low
Master output valid
Master input setup
Master output hold
Tri-state enable
Tri-state disable
I/O
I/O Type
O
1V8
I
1V8
O
1V8
O
1V8
Rev 1.1
Min
Typ
-
-
38
-
17
-
17
-
-5
-
0
-
0
-
-5
-
-5
-
Reset State
Z
Z
Z
Z
Baseband Specification
Max
Unit
26
MHz
-
ns
-
ns
-
ns
5
ns
3
ns
3
ns
5
ns
5
ns
Description
SPI Serial Clock
SPI Serial input
SPI Serial output
SPI Chip Select
January 21, 2015
48
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