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Hardware Integration Guide
6.15.2.1.1.
The PCM data is 8 kHz and 16 bits with the following PDM bit format:
PCM_DIN – SDDD DDDD DDDD DDVV
PCM_DOUT – SDDD DDDD DDDD DDVV
Where:
S – Signed bit
D – Data
V – Volume padding
6.15.2.1.2.
The table and drawings below illustrate the PCM signals timing when the AirPrime AR7558 module is
operating in Primary PCM mode.
Table 60.
Primary PCM Timing
Parameter
Description
T(sync)
PCM_FS cycle time
T(synch)
PCM_FS high time
T(syncl)
PCM_FS low time
T(clk)
PCM_CLK cycle time
T(clkh)
PCM_CLK high time
T(clkl)
PCM_CLK low time
T(susync)
PCM_FS setup time high before falling edge of PCM_CLK
T(hsync)
PCM_FS Hold time after falling edge of PCM_CLK
T(sudin)
PCM_DIN setup time before falling edge of PCM_CLK
T(hdin)
PCM_DIN hold time after falling edge of PCM_CLK
T(pdout)
Delay from PCM_CLK rising to PCM_DOUT valid
T(zdout)
Delay from PCM_CLK falling to PCM_DOUT HIGH-Z
Figure 18.
PCM_FS Timing Diagram (2048 kHz Clock)
4116922
PCM Data format
Primary PCM Timing
Rev 1.1
Baseband Specification
Min
Typ
Max
-
125
-
-
488
-
-
124.5
-
-
488
-
-
244
-
-
244
-
-
122
-
-
-
366
60
-
-
60
-
-
-
-
60
-
-
60
January 21, 2015
unit
µs
ns
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
43
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