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HSS-730/830 & UFD505/515 SERVICE MANUAL
3.
Hardware
This section describes the entire architecture and an individual module of the STB hardware.
3.1. System Block Diagram
The hardware is modularly designed to support as many markets as possible while minimizing the
burden on developing the derivative hardware. This approach also enables the derivative hardware
to be quickly developed in order to meet a variety of user demands. The Block Diagram of page 8
depicts the System Block Diagram.
3.2. Main Board Clock Diagram
3.2.1. Clock Diagram for CI Model
l
27MHz System Clock
VCXO 27Mhz
3.2.2. Clock Diagram for FTA Model
l
27MHz System Clock
VCXO 27MHz
STi5518 Pin 120
CIMAX /STV0700 Pin 35
STi5518 Pin 120
HDT DVB SATELLITE STB
121.5MHz
to SDRAM Pin 38
121.5MHz
to SDRAM Pin 38
Page
7
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