Timing I/O Circuitry; Figure 4-4. Digital I/O Circuitry Block Diagram - National Instruments Corporation DAQCard-500 User Manual

Theory of Operation
I/O RD
I/O WR

Timing I/O Circuitry

The DAQCard-500 uses an MSM82C54 counter/timer integrated circuit for data acquisition
timing and for general-purpose timing I/O functions. Counters 1 and 2 of the MSM82C54 are
available for general use, but counter 0 is used internally for data acquisition timing. The gate
signal of counter 1 is internally pulled up and is always active. Figure 4-5 shows a block
diagram of both groups of timing I/O circuitry.
DAQCard-500 User Manual
4
/
Digital
Input
Register
4
/
Digital
Output
Register

Figure 4-4. Digital I/O Circuitry Block Diagram

4
/
4
/
4-6 © National Instruments Corporation
Chapter 4
DIN <0..3>
DOUT<0..3>