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Alpha Data XRM(2)-DAC-D4/1G User Manual

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XRM(2)-DAC-D4/1G User Guide
Document Revision: 2.2
Mar 8, 2018

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Summary of Contents for Alpha Data XRM(2)-DAC-D4/1G

  • Page 1 XRM(2)-DAC-D4/1G User Guide Document Revision: 2.2 Mar 8, 2018...
  • Page 2 XRM(2)-DAC-D4/1G User Guide V2.2 - Mar 8, 2018 © 2018 Copyright Alpha Data Parallel Systems Ltd. All rights reserved. This publication is protected by Copyright Law, with all rights reserved. No part of this publication may be reproduced, in any shape or form, without prior written consent from Alpha Data Parallel Systems Ltd.

  • Page 3: Table Of Contents

    Block Diagram ..........................1 XRM and XRM2 ..........................4 1.2.1 Signalling Voltage ........................4 Build Level ............................. 4 Alpha Data SDK Versions ......................4 Xilinx Tool Versions ........................4 ISE Projects ........................... 4 1.6.1 Structure ............................ 4 Vivado Projects ..........................6 1.7.1...
  • Page 4 XRM(2)-DAC-D4/1G User Guide V2.2 - Mar 8, 2018 3.3.7 Sine Test ..........................25 Register Description ........................26 FPGA_CNTRL_REG (0x00) ......................28 FPGA_STATUS_REG (0x01) ...................... 30 CNTR_STAT_REG (0x02) ......................32 I_DDS_REG (0x03) ........................34 Q_DDS_REG (0x04) ........................36 I_INC_REG (0x05) ........................38 Q_INC_REG (0x06) ........................

  • Page 5: Introduction

    V2.2 - Mar 8, 2018 1 Introduction Alpha Data provide three variants of a fast analogue signal generation card operating at sampling frequencies up to 1 GHz, based on the DAC5681, DAC5681Z and DAC5682Z devices from Texas Instruments. The DAC5681 provides a non-interpolating architecture for wideband signal generation.
  • Page 6 XRM(2)-DAC-D4/1G User Guide V2.2 - Mar 8, 2018 External reference, internally synthesised clock, giving integer sub-divisions of 1GHz. A pair of LVTTL outputs ('TRIG' and 'AUX') is provided (3V3 signal levels) via SMA connectors. In addition, two direct connections to FPGA pins via UFL connectors are also available for fast signalling interconnect between multiple DAC cards or other devices.

  • Page 7: Figure 1 Block Diagram

    XRM(2)-DAC-D4/1G User Guide V2.2 - Mar 8, 2018 Figure 1 : Block Diagram Introduction Page 3 xrm-dac-d4-1g-manual_v2_2.pdf...

  • Page 8: Xrm And Xrm2

    3. 1.4 Alpha Data SDK Versions All VHDL code for legacy boards is built using Alpha Data's SDK version 4.9.3. This SDK version is frozen at this revision. All VHDL code for current boards uses Alpha Data's ADMXRCG3SDK version 1.7.0.

  • Page 9: Figure 2 Default Project Structure

    XRM(2)-DAC-D4/1G User Guide V2.2 - Mar 8, 2018 project (highlighted). Figure 2 : Default Project Structure Introduction Page 5 xrm-dac-d4-1g-manual_v2_2.pdf...

  • Page 10: Vivado Projects

    TCL files are used to generate project files and folder structures. This uses the same 'design-model-device' syntax as the Alpha Data SDK examples, where the 'design' equates to the XRM type, the 'model' equates to the ADMXRC board type and the 'device' equates to the specific FPGA on the FPGA card.
  • Page 11 XRM(2)-DAC-D4/1G User Guide V2.2 - Mar 8, 2018 The main Vivado folder contains three files - genxpr.bat, genxpr.tcl, makexpr.tcl plus a folder named after each supported model of board; currently there are only two models supported, the 7K1 and the 7V1.The model folders contain TCL files that are specific to the design.

  • Page 12: Figure 4 Vivado Files

    XRM(2)-DAC-D4/1G User Guide V2.2 - Mar 8, 2018 Figure 4 : Vivado Files It is strongly recommended to retain the folder structure shown in the main Vivado folder in order to ensure that TCL files provided work correctly. Alterations to this structure will entail the need for extensive modification of paths/files embedded in the scripts.

  • Page 13: Hardware

    XRM(2)-DAC-D4/1G User Guide V2.2 - Mar 8, 2018 2 Hardware 2.1 Hardware Operation The application must first configure the FPGA with the bit stream using the standard functions provided in the SDK before any hardware or FPGA registers can be accessed via the local bus .

  • Page 14: Dac Programming

    XRM(2)-DAC-D4/1G User Guide V2.2 - Mar 8, 2018 2.4 DAC Programming The register values following a reset of the DAC require to be modified for correct operation. Firstly the interface must be set to operate in 4-wire mode as noted above. For the DAC 5681 this is essentially all that needs to be done, since the clock is set up explicitly by the application, which in turn configures the DLL settings and re-starts the DAC DLL.

  • Page 15: Dac Selftest

    XRM(2)-DAC-D4/1G User Guide V2.2 - Mar 8, 2018 can be used in this mode.Consult the factory for the availability of custom VCXO frequencies for applications requiring other frequencies. The external signal source can be used in place of the VCXO as the clock driving the distribution section for the DAC so can be used as the DAC clock directly or integer divisions of this source can be used.The maximum...

  • Page 16: Multiple Dac Synchronisation

    XRM(2)-DAC-D4/1G User Guide V2.2 - Mar 8, 2018 data output. This signal is normally controlled by the hardware pin (see register description below), but can be controlled via the serial interface. SYNC is set low prior to clock adjustment ( and the FPGA-generated data forced to output a zero level) to minimise transients on the DAC outputs.

  • Page 17: Low Frequency Operation

    XRM(2)-DAC-D4/1G User Guide V2.2 - Mar 8, 2018 driven by the BUFR signal derived from the BUFIO clock to maintain timing alignment. The global clock signal which drives the data generation hardware (FABRCLK) runs at the same speed as this. The DCM aligns the global clock with these clocks and a constraint on the path lengths when crossing the clock domains ensures that data has the required setup and hold.

  • Page 18: Clocking On Virtex6, Kintex7 And Virtex7

    XRM(2)-DAC-D4/1G User Guide V2.2 - Mar 8, 2018 Figure 6 : Low frequency clocking scheme Here the data generation in the FPGA runs at the same speed as the DAC sample clock fed to the DACs, so the FPGA generates 1 sample per DAC sample clock cycle instead of 4 samples at 0.25 *DAC sample clock cycle.

  • Page 19: Data Generation

    XRM(2)-DAC-D4/1G User Guide V2.2 - Mar 8, 2018 Figure 7 : Kintex 7 Virtex 7 Clocking Scheme The remaining clock inputs are used for clock monitoring and diagnostic purposes only 2.13 Data Generation Each DAC receives data via a 16-bit DDR interface, plus DCLK, generated by the data source synchronously with the data.

  • Page 20: Board Layout

    XRM(2)-DAC-D4/1G User Guide V2.2 - Mar 8, 2018 2.15 Board Layout Figure 8 : XRM(2)-DAC-D4-1G Layout Page 16 Hardware xrm-dac-d4-1g-manual_v2_2.pdf...

  • Page 21: Table 1 Sma And Ufl Connectors

    XRM(2)-DAC-D4/1G User Guide V2.2 - Mar 8, 2018 Connector Function Signal Levels I channel DAC output +/500 mV (+4 dBm) Q channel DAC output +/500 mV (+4 dBm) Ext. Clock input 0dBm +6 dB AUX Dig I/0 3v3 LVTTL TRIG Dig I/O...

  • Page 22: Vhdl Structure

    XRM(2)-DAC-D4/1G User Guide V2.2 - Mar 8, 2018 3 VHDL Structure 3.1 Introduction The basic data flow is illustrated in figures 5 and 7 above. The clock components provide a clock for the output stage at the appropriate rate and the global clock for running the data generation circuitry. Each channel has its own data generation, DCLK and SYNC generation circuit under control of the host via the local bus interface.

  • Page 23: Local Bus Interface

    XRM(2)-DAC-D4/1G User Guide V2.2 - Mar 8, 2018 generation is performed at the FABRCLK rate, with appropriate synchronisation of control signals from the local clock domain. The FPGA data generation drives a 4:1 OSERDES, so must generate four samples of data for each cycle of FABRCLK.

  • Page 24: Digital I/O

    XRM(2)-DAC-D4/1G User Guide V2.2 - Mar 8, 2018 ignored. At the end of the transfer process the data read from the devices is registered on the read data port at the end of the handshake sequence. This data is held until the next read sequence is triggered.

  • Page 25: Virtex6, Virtex7, Kintex7

    XRM(2)-DAC-D4/1G User Guide V2.2 - Mar 8, 2018 Address decoding uses address bits 22 to 19, with bit 23 zero and register addresses within each page are decoded using local address bits 9 to 2 for 32 bit accesses. 3.2.7.2 Virtex6, Virtex7, Kintex7 All registers are 32 bits wide but are 128-bit aligned, so addresses A1 to A3 inclusive are unused and register addresses within each page are decoded using local address bits 11 to 4.

  • Page 26: Waveform Generator Operation

    XRM(2)-DAC-D4/1G User Guide V2.2 - Mar 8, 2018 3.3 Waveform Generator Operation The example code provides a number of built-in waveform generation options. In each case the fact that FABRCLK (which drives the FPGA fabric) runs at one quarter of the DAC sample clock frequency requires that four samples are produced by the generators on each FABRCLK cycle so typically four generators of each type, acting in parallel, are required.

  • Page 27: Ramp Waveform Generator

    XRM(2)-DAC-D4/1G User Guide V2.2 - Mar 8, 2018 Once the required register value Val is calculated as above, the actual increment applied to each core is 4*Val, with the inital phase accumulator value for each core offset fromt the preceding one by Val. Thus core 0 produces the values for sample numbers 0,4,8 ..., core 1 produces the values for sample numbers 1,5,9 .., core...

  • Page 28: Square/Pulse Waveform Generator

    XRM(2)-DAC-D4/1G User Guide V2.2 - Mar 8, 2018 3.3.4 Square/Pulse Waveform Generator For square wave generation, the waveform output is set to the mark value for a given number of FABRCLK cycles and is then followed by the space value for separetely specified number of clock cycles.

  • Page 29: Self Test Pattern

    XRM(2)-DAC-D4/1G User Guide V2.2 - Mar 8, 2018 Burst mode is used to extend the reptition rates achievable by means of a 16-bit count register C , where C is the count of repetitions of the ARB length L (the RAM end address). When Burst mode is enabled, the L samples from the RAM are read out;...

  • Page 30: Register Description

    XRM(2)-DAC-D4/1G User Guide V2.2 - Mar 8, 2018 4 Register Description All data accesses are 32 bits wide; for writes, unused bits are ignored whilst on reads unused bits are always mapped as a logic low. A total of 30 registers are used, although not all bits are active controls.
  • Page 31 XRM(2)-DAC-D4/1G User Guide V2.2 - Mar 8, 2018 Register Name Address PHASE_REG 0X1F Register Description Page 27 xrm-dac-d4-1g-manual_v2_2.pdf...

  • Page 32: Fpga_Cntrl_Reg (0X00)

    XRM(2)-DAC-D4/1G User Guide V2.2 - Mar 8, 2018 4.1 FPGA_CNTRL_REG (0x00) The control register provides various bits for controlling timing and resets. D31 to D24: D31 Clock align request, rising edge triggers alignment. D30 Select HF DCM when low (default), LF DCM when high.

  • Page 33: Table 2 Clock Muxing (D25,D24)

    XRM(2)-DAC-D4/1G User Guide V2.2 - Mar 8, 2018 D7 to D0: I channel signal select bit 0,lsb I channel signal select bit 3, msb I channel output enable; 0 = all zeroes transmitted by FPGA, 1 = FPGA generator data transmitted to DAC.

  • Page 34: Fpga_Status_Reg (0X01)

    XRM(2)-DAC-D4/1G User Guide V2.2 - Mar 8, 2018 4.2 FPGA_STATUS_REG (0x01) The read-only status register provides read back of the various system status bits for control and diagnostic use. D31 to D24: D31 XRM pcb revision setting, msb D30 XRM pcb revision setting bit 2...
  • Page 35 XRM(2)-DAC-D4/1G User Guide V2.2 - Mar 8, 2018 D7 to D0: D2 I channel initialisation sequence flag (1=init sequence running). I channel DAC serial interface complete flag (1=complete, set at end of transfer and cleared by start of next transfer).

  • Page 36: Cntr_Stat_Reg (0X02)

    XRM(2)-DAC-D4/1G User Guide V2.2 - Mar 8, 2018 4.3 CNTR_STAT_REG (0x02) Data read from this read-only location returns the detection counter bits for each of the four clock inputs where instantiated in the FPGA. D31 to D24: D31 unused D30 unused...
  • Page 37 XRM(2)-DAC-D4/1G User Guide V2.2 - Mar 8, 2018 D7 to D0: D2 Clock input X, detect counter D2 D1 Clock input X, detect counter D1 D0 Clock input X, detect counter D0, lsb Register Description Page 33 xrm-dac-d4-1g-manual_v2_2.pdf...

  • Page 38: I_Dds_Reg (0X03)

    XRM(2)-DAC-D4/1G User Guide V2.2 - Mar 8, 2018 4.4 I_DDS_REG (0x03) Data written to this location sets the DDS phase accumulator increment to determine the output frequency based on the DAC sample clock frequency. The actual output frequency is related to the signed 32-bit register value by:...
  • Page 39 XRM(2)-DAC-D4/1G User Guide V2.2 - Mar 8, 2018 D6 DDS phase increment D6 D5 DDS phase increment D5 D4 DDS phase increment D4 D3 DDS phase increment D3 D2 DDS phase increment D2 D1 DDS phase increment D1 D0 DDS phase increment D0, lsb...

  • Page 40: Q_Dds_Reg (0X04)

    XRM(2)-DAC-D4/1G User Guide V2.2 - Mar 8, 2018 4.5 Q_DDS_REG (0x04) Data written to this location sets the DDS phase accumulator increment to determine the output frequency based on the DAC sample clock frequency. The actual output frequency is related to the signed 32-bit register value by:...
  • Page 41 XRM(2)-DAC-D4/1G User Guide V2.2 - Mar 8, 2018 D6 DDS phase increment D6 D5 DDS phase increment D5 D4 DDS phase increment D4 D3 DDS phase increment D3 D2 DDS phase increment D2 D1 DDS phase increment D1 D0 DDS phase increment D0, lsb...

  • Page 42: I_Inc_Reg (0X05)

    XRM(2)-DAC-D4/1G User Guide V2.2 - Mar 8, 2018 4.6 I_INC_REG (0x05) Used for both simple ramp (sawtooth) and triangle generation. Data written to this register sets the increment value for the ramp on each clock cycles. For ramp generation, the...
  • Page 43 XRM(2)-DAC-D4/1G User Guide V2.2 - Mar 8, 2018 D15 to D8: D8 Ramp increment, Triangle end value D8 D7 to D0: D7 Ramp increment, Triangle end value D7 D6 Ramp increment, Triangle end value D6 D5 Ramp increment, Triangle end value D5...

  • Page 44: Q_Inc_Reg (0X06)

    XRM(2)-DAC-D4/1G User Guide V2.2 - Mar 8, 2018 4.7 Q_INC_REG (0x06) Used for both simple ramp (sawtooth) and triangle generation. Data written to this register sets the increment value for the ramp on each clock cycle. The increment for ramp...
  • Page 45 XRM(2)-DAC-D4/1G User Guide V2.2 - Mar 8, 2018 D15 to D8: D8 Ramp increment,Triangle end value D8 D7 to D0: D7 Ramp increment,Triangle end value D7 D6 Ramp increment,Triangle end value D6 D5 Ramp increment,Triangle end value D5 D4 Ramp increment,Triangle end value D4...

  • Page 46: Synth_Cntrl_Reg (0X07)

    XRM(2)-DAC-D4/1G User Guide V2.2 - Mar 8, 2018 4.8 SYNTH_CNTRL_REG (0x07) Used to specify the data and addresses for reads and writes via the serial interface for the AD9510 synthesiser. The bottom 8 bits are the write data, with the next 8 bits forming the address for reads and writes. The top 16 bits of this word (read data and status bits) are read-only.
  • Page 47 XRM(2)-DAC-D4/1G User Guide V2.2 - Mar 8, 2018 D7 to D0: D4 D4 serial write data D3 D3 serial write data D2 D2 serial write data D1 D1 serial write data D0 D0 serial write data Register Description Page 43...

  • Page 48: Synth_Strb_Reg (0X08)

    XRM(2)-DAC-D4/1G User Guide V2.2 - Mar 8, 2018 4.9 SYNTH_STRB_REG (0x08) D31 to D24: D31 unused D30 unused D29 unused D28 unused D27 unused D26 unused D25 unused D24 unused D23 to D16: D23 unused D22 unused D21 unused D20 unused...
  • Page 49 XRM(2)-DAC-D4/1G User Guide V2.2 - Mar 8, 2018 D7 to D0: Write strobe-setting this bit high triggers a synthesiser serial interface write cycle using the values in the control register. This bit is self-clearing. Read strobe-setting this bit high triggers a synthesiser serial interface read cycle.

  • Page 50: Idac_Cntrl_Reg (0X09)

    XRM(2)-DAC-D4/1G User Guide V2.2 - Mar 8, 2018 4.10 IDAC_CNTRL_REG (0x09) Used to specify the data and addresses for reads and writes via the serial interface for the I channel DAC. The bottom 8 bits are the write data, with the next 8 bits forming the address. The top 16 bits of this word (read data and status bits) are read-only.
  • Page 51 XRM(2)-DAC-D4/1G User Guide V2.2 - Mar 8, 2018 D7 to D0: D4 D4 serial write data D3 D3 serial write data D2 D2 serial write data D1 D1 serial write data D0 D0 serial write data Register Description Page 47...

  • Page 52: Idac_Strb_Reg (0X0A)

    XRM(2)-DAC-D4/1G User Guide V2.2 - Mar 8, 2018 4.11 IDAC_STRB_REG (0x0A) Triggers serial reads, writes or forces the initialisation sequence to be active on the serial interface for the I channel DAC. Write only D31 to D24: D31 Unused D30 Unused...
  • Page 53 XRM(2)-DAC-D4/1G User Guide V2.2 - Mar 8, 2018 D7 to D0: Init strobe-setting this bit high triggers a IDAC serial interface initialisation (write) sequence. This bit is self-clearing. Write strobe-setting this bit high triggers a IDAC serial interface write cycle using the values in the control register. This bit is self-clearing.

  • Page 54: Qdac_Cntrl_Reg (0X0B)

    XRM(2)-DAC-D4/1G User Guide V2.2 - Mar 8, 2018 4.12 QDAC_CNTRL_REG (0x0B) Used to specify the data and addresses for reads and writes via the serial interface for the Q channel DAC. The bottom 8 bits are the write data, with the next 8 bits forming the address. The top 16 bits of this word (read data and status bits) are read-only.
  • Page 55 XRM(2)-DAC-D4/1G User Guide V2.2 - Mar 8, 2018 D7 to D0: D4 D4 serial write data D3 D3 serial write data D2 D2 serial write data D1 D1 serial write data D0 D0 serial write data Register Description Page 51...

  • Page 56: Qdac_Strb_Reg (0X0C)

    XRM(2)-DAC-D4/1G User Guide V2.2 - Mar 8, 2018 4.13 QDAC_STRB_REG (0x0C) Triggers serial reads, writes or forces the initialisation sequence to be active on the serial interface for the Q channel DAC. Write only D31 to D24: D31 Unused D30 Unused...
  • Page 57 XRM(2)-DAC-D4/1G User Guide V2.2 - Mar 8, 2018 D7 to D0: Init strobe-setting this bit high triggers a QDAC serial interface initialisation (write) sequence. This bit is self-clearing. Write strobe-setting this bit high triggers a QDAC serial interface write cycle using the values in the control register. This bit is self- clearing.

  • Page 58: Device_Reg (0X0D)

    XRM(2)-DAC-D4/1G User Guide V2.2 - Mar 8, 2018 4.14 DEVICE_REG (0x0D) This register provides 4 separate bytes for controlling the initialisation sequence and the DLL setting ( clock-frequency dependent) used in the DAC automatic initialisation sequence. The top 16 bits (1 byte for each channel) are used to specify the DLL setting forced into the DAC serial initialisation stream to handle differences between different DACs.
  • Page 59 XRM(2)-DAC-D4/1G User Guide V2.2 - Mar 8, 2018 D6 I channel DAC type code D6 D5 I channel DAC type code D5 D4 I channel DAC type code D4 D3 I channel DAC type code D3 D2 I channel DAC type code D2...

  • Page 60: I_Ddsinit_Reg(0X0E)

    XRM(2)-DAC-D4/1G User Guide V2.2 - Mar 8, 2018 4.15 I_DDSINIT_REG(0x0E) This register provides a mechanism to specify the phase offset of the I channel from that of the default 0 degrees when operating with the DDS signal (sine) selected. Data is scaled in the same way as frequency increments The DDS generator has a 32-bit phase accumulator;...
  • Page 61 XRM(2)-DAC-D4/1G User Guide V2.2 - Mar 8, 2018 D6 D6 DDS phase bit D5 D5 DDS phase bit D4 D4 DDS phase bit D3 D3 DDS phase bit D2 D2 DDS phase bit D1 D1 DDS phase bit D0 D0 DDS phase bit lsb...

  • Page 62: Q_Ddsinit_Reg(0X0F)

    XRM(2)-DAC-D4/1G User Guide V2.2 - Mar 8, 2018 4.16 Q_DDSINIT_REG(0x0F) This register provides a mechanism to specify the phase offset of the Q channel from that of the default 0 degrees when operating with the DDS signal (sine) selected. Data is scaled in the same way as frequency increments The DDS generator has a 32-bit phase accumulator;...
  • Page 63 XRM(2)-DAC-D4/1G User Guide V2.2 - Mar 8, 2018 D6 D6 DDS phase bit D5 D5 DDS phase bit D4 D4 DDS phase bit D3 D3 DDS phase bit D2 D2 DDS phase bit D1 D1 DDS phase bit D0 D0 DDS phase bit lsb...

  • Page 64: Ipattern_Reg (0X10)

    XRM(2)-DAC-D4/1G User Guide V2.2 - Mar 8, 2018 4.17 IPATTERN_REG (0x10) This register provides two 16 bit values which are used to control data generation for triangle and pulse (square) waveforms and also serve to specify the data for self test operation on the I channel.
  • Page 65 XRM(2)-DAC-D4/1G User Guide V2.2 - Mar 8, 2018 D15 to D8: D10 Pos slope bit 10, Mark level bit 10 D9 Pos slope bit 9, Mark level bit 9 D8 Pos slope bit 8, Mark level bit 8 D7 to D0:...

  • Page 66: Qpattern_Reg (0X11)

    XRM(2)-DAC-D4/1G User Guide V2.2 - Mar 8, 2018 4.18 QPATTERN_REG (0x11) This register provides two 16 bit values which are used to control data generation for triangle and pulse (square) waveforms and also serve to specify the data for self test operation on the Q channel.
  • Page 67 XRM(2)-DAC-D4/1G User Guide V2.2 - Mar 8, 2018 D15 to D8: D10 Pos slope bit 10, Mark level bit 10 D9 Pos slope bit 9, Mark level bit 9 D8 Pos slope bit 8, Mark level bit 8 D7 to D0:...

  • Page 68: Ipattern_Reg2 (0X12)

    XRM(2)-DAC-D4/1G User Guide V2.2 - Mar 8, 2018 4.19 IPATTERN_REG2 (0x12) This register provides two 16 bit values which are used to control data generation for triangle and pulse (square) waveforms and also serve to specify the data for self test operation on the I channel.
  • Page 69 XRM(2)-DAC-D4/1G User Guide V2.2 - Mar 8, 2018 Note that pulse and triangle periods are constrained to be integer multiples of FABRCLK cycles. Register Description Page 65 xrm-dac-d4-1g-manual_v2_2.pdf...

  • Page 70: Qpattern_Reg2 (0X13)

    XRM(2)-DAC-D4/1G User Guide V2.2 - Mar 8, 2018 4.20 QPATTERN_REG2 (0x13) This register provides two 16 bit values which are used to control data generation for triangle and pulse (square) waveforms and also serve to specify the data for self test operation on the Q channel.
  • Page 71 XRM(2)-DAC-D4/1G User Guide V2.2 - Mar 8, 2018 Note that pulse and triangle periods are constrained to be integer multiples of FABRCLK cycles. Register Description Page 67 xrm-dac-d4-1g-manual_v2_2.pdf...

  • Page 72: Meas0_Val_Reg (0X14)

    XRM(2)-DAC-D4/1G User Guide V2.2 - Mar 8, 2018 4.21 MEAS0_VAL_REG (0x14) This register provides a 24 bit measurement (determined by CKMEAS_WIDTH) of the period of the unused clock input from the synthesiser for determining the frequency of the internal or external clock.
  • Page 73 XRM(2)-DAC-D4/1G User Guide V2.2 - Mar 8, 2018 D7 to D0: D5 D5 gate-time multiplier D4 D4 gate-time multiplier D3 D3 gate-time multiplier D2 D2 gate-time multiplier D1 D1 gate-time multiplier D0 D0 gate-time multiplier LSB Register Description Page 69...

  • Page 74: Meas1_Val_Reg (0X15)

    XRM(2)-DAC-D4/1G User Guide V2.2 - Mar 8, 2018 4.22 MEAS1_VAL_REG (0x15) This register provides a 24 bit measurement ( determined by CKMEAS_WIDTH) of the period of the transitions on the synthesiser STATUS signal for frequency measurements of the ref oscillator etc.
  • Page 75 XRM(2)-DAC-D4/1G User Guide V2.2 - Mar 8, 2018 D7 to D0: D5 D5 gate-time multiplier D4 D4 gate-time multiplier D3 D3 gate-time multiplier D2 D2 gate-time multiplier D1 D1 gate-time multiplier D0 D0 gate-time multiplier LSB Register Description Page 71...

  • Page 76: Meas2_Val_Reg (0X16)

    XRM(2)-DAC-D4/1G User Guide V2.2 - Mar 8, 2018 4.23 MEAS2_VAL_REG (0x16) Address allocated for frequency measurements but unused Unused bits read as 0 D31 to D24: D31 N/A D30 N/A D29 N/A D28 N/A D27 N/A D26 N/A D25 N/A...
  • Page 77 XRM(2)-DAC-D4/1G User Guide V2.2 - Mar 8, 2018 D7 to D0: D2 N/A D1 N/A D0 N/A Register Description Page 73 xrm-dac-d4-1g-manual_v2_2.pdf...

  • Page 78: Freerun_Cnt_Reg (0X17)

    XRM(2)-DAC-D4/1G User Guide V2.2 - Mar 8, 2018 4.24 FREERUN_CNT_REG (0x17) This register is a free-running 32bit counter updated at 1 us intervals for timing use. All bits are read-only and are used by software routines for implementing time delays with 1 us resolution.
  • Page 79 XRM(2)-DAC-D4/1G User Guide V2.2 - Mar 8, 2018 D7 to D0: D2 D2 free-running counter D1 D1 free-running counter D0 D0 free-running counter LSB, changes at 1 us intervals Register Description Page 75 xrm-dac-d4-1g-manual_v2_2.pdf...

  • Page 80: I_Arbwrite_Reg (0X18)

    XRM(2)-DAC-D4/1G User Guide V2.2 - Mar 8, 2018 4.25 I_ARBWRITE_REG (0x18) Writes to this register are copied into the IARB memory to form two 16 bit samples, with the earliest sample in the lower word. D31 to D24: D31 bit D15 of 16-bit sample number N+1...
  • Page 81 XRM(2)-DAC-D4/1G User Guide V2.2 - Mar 8, 2018 D7 to D0: D2 bit D2 D1 bit D1 D0 D0, LSB of 16-bit sample number N Register Description Page 77 xrm-dac-d4-1g-manual_v2_2.pdf...

  • Page 82: Q_Arbwrite_Reg (0X19)

    XRM(2)-DAC-D4/1G User Guide V2.2 - Mar 8, 2018 4.26 Q_ARBWRITE_REG (0x19) Writes to this register are copied into the QARB memory to form two 16 bit samples, with the earliest sample in the lower word. D31 to D24: D31 bit D15 of 16-bit sample number N+1...
  • Page 83 XRM(2)-DAC-D4/1G User Guide V2.2 - Mar 8, 2018 D7 to D0: D2 bit D2 D1 bit D1 D0 D0, LSB of 16-bit sample number N Register Description Page 79 xrm-dac-d4-1g-manual_v2_2.pdf...

  • Page 84: Arb _Cntrl_Reg (0X1A)

    XRM(2)-DAC-D4/1G User Guide V2.2 - Mar 8, 2018 4.27 ARB _CNTRL_REG (0x1A) This register controls loading, running and synchronisation of the arbitrary waveform generators. D31 to D24: D31 N/A D30 N/A D29 N/A D28 N/A D27 N/A D26 MSB of ARB sequence length...
  • Page 85 XRM(2)-DAC-D4/1G User Guide V2.2 - Mar 8, 2018 D7 to D0: D2 Load enable for IARB length value D1 Burst/continuous select for IARB sequence D0 Run enable for IARB sequence Register Description Page 81 xrm-dac-d4-1g-manual_v2_2.pdf...

  • Page 86: Arb _Tick_Reg (0X1B)

    XRM(2)-DAC-D4/1G User Guide V2.2 - Mar 8, 2018 4.28 ARB _TICK_REG (0x1B) This register provides two 16 bit values for use with the ARB generator. The top 16 bits determine the marker width in FABRCLK cycles, although this is limites to 4096 ( 12 bits) max by the hardware.The bottom 16 bits determine the repetition rate of the ARB waveform, which consists of 1 cycle of data from the ARB RAM followed by (N-1) cycles of zero output, each the same length as the ARB RAM waveform.
  • Page 87 XRM(2)-DAC-D4/1G User Guide V2.2 - Mar 8, 2018 D7 to D0: D3 D3 repeat rate control D2 D2 repeat rate control D1 D1 repeat rate control D0 LSB of 16-bit repeat rate control for ARB sequence. Register Description Page 83...

  • Page 88: Auxcntrl_Reg (0X1E)

    XRM(2)-DAC-D4/1G User Guide V2.2 - Mar 8, 2018 4.29 AUXCNTRL_REG (0x1E) Miscellaneous control bits and mark/space duration fine control for pulse waveforms. D31 to D24: D31 Unused D30 Unused D29 Unused D28 Unused D27 Unused D26 Unused D25 Unused D24 Unused...
  • Page 89 XRM(2)-DAC-D4/1G User Guide V2.2 - Mar 8, 2018 D7 to D0: XRM board revision (high for rev2 and rev1 boards polarity correction - redundant) D0 Phase value mux The fine control bits for the I and Q channels allow extension of the mark duration in increments of the DACCLK period.

  • Page 90: Phase_Value_Reg (0X1F)

    XRM(2)-DAC-D4/1G User Guide V2.2 - Mar 8, 2018 4.30 PHASE_VALUE_REG (0x1F) This register provides two 16 bit values which are sign-extended versions of the 9 bit phase alignment settings. By default. the values returned are the mid-point of the phase window ( lower 16 bits) and the width of the window (upper 16 bits), which is centred on the mid-point value.
  • Page 91 XRM(2)-DAC-D4/1G User Guide V2.2 - Mar 8, 2018 D6 D6 mid point (start point) of valid DCM phase window D5 D5 mid point (start point) of valid DCM phase window D4 D4 mid point (start point) of valid DCM phase window...
  • Page 92 XRM(2)-DAC-D4/1G User Guide V2.2 - Mar 8, 2018 Revision History Date Revision Nature of Change Draft 26/02/09 First issue with release 1.2 of code 03/04/09 Added signalling voltage, alternative clocking scheme and 12/08/09 updated register bits Fixed minor typos. 14/09/09 Updated to reflect code changes for release 2.0 renamed...

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