Alpha Data XRM(2)-DAC-D4/1G Manuals

Manuals and User Guides for Alpha Data XRM(2)-DAC-D4/1G. We have 1 Alpha Data XRM(2)-DAC-D4/1G manual available for free PDF download: User Manual

Alpha Data XRM(2)-DAC-D4/1G User Manual

Alpha Data XRM(2)-DAC-D4/1G User Manual (92 pages)

Brand: Alpha Data | Category: Control Unit | Size: 2 MB

Table of Contents

Table of Contents
3
1 Introduction

5
- Block Diagram
  5
- Figure 1 Block Diagram
  7
- XRM and XRM2
  8
  - Signalling Voltage
    8
- Build Level
  8
- Alpha Data SDK Versions
  8
- Xilinx Tool Versions
  8
- ISE Projects
  8
  - Structure
    8
  - Figure 2 Default Project Structure
    9
- Vivado Projects
  10
  - Vivado Folder Structure
    10
  - Figure 3 Vivado Project Structure
    10
  - Figure 4 Vivado Files
    12
  - V2.2 - Mar
    12
2 Hardware

13
- Hardware Operation
  13
- Connector Signals
  13
- DAC Serial Interface
  13
- DAC Programming
  14
- Synthesiser Serial Interface
  14
- Synthesiser Programming
  14
- DAC Selftest
  15
  - Pattern Testing
    15
  - Fifo Test
    15
  - Selftest
    15
- DAC DLL Control
  15
- DAC Sync
  15
- Multiple DAC Synchronisation
  16
- Clocking on Virtex4, Virtex5
  16
  - Figure 5 Virtex 4 Virtex 5 Clocking Scheme
    16
  - Low Frequency Operation
    17
- Clocking on Virtex6, Kintex7 and Virtex7
  18
- Figure 6 Low Frequency Clocking Scheme
  18
- Data Generation
  19
- Performance
  19
- Figure 7 Kintex 7 Virtex 7 Clocking Scheme
  19
- Board Layout
  20
- Figure 8 XRM(2)-DAC-D4-1G Layout
  20
- Table 1 SMA and UFL Connectors
  21
3 VHDL Structure

22
- Introduction
  22
- Major HDL Components
  22
  - Clock Generation and Alignment
    22
  - Data Generation and Output
    22
  - Local Bus Interface
    23
    
    Virtex4, Virtex5
    23
    
    Virtex6, Virtex7, Kintex7
    23
  - Serial Control
    23
  - Digital I/O
    24
  - General Purpose I/O
    24
  - Host Access Via Local Bus
    24
    
    Virtex4, Virtex5
    24
    
    Virtex6, Virtex7, Kintex7
    25
- Waveform Generator Operation
  26
  - Sine Waveform Generator
    26
  - Figure 9 Waveform Selection Diagram
    26
  - Ramp Waveform Generator
    27
  - Triangle Waveform Generator
    27
  - Square/Pulse Waveform Generator
    28
  - Arbitrary Waveform Generator
    28
  - Self Test Pattern
    29
  - Sine Test
    29
4 Register Description

30
- FPGA_CNTRL_REG (0X00)
  32
- Table 2 Clock Muxing (D25,D24)
  33
- FPGA_STATUS_REG (0X01)
  34
- CNTR_STAT_REG (0X02)
  36
- I_DDS_REG (0X03)
  38
- Q_DDS_REG (0X04)
  40
- I_INC_REG (0X05)
  42
- Q_INC_REG (0X06)
  44
- SYNTH_CNTRL_REG (0X07)
  46
- SYNTH_STRB_REG (0X08)
  48
- IDAC_CNTRL_REG (0X09)
  50
- IDAC_STRB_REG (0X0A)
  52
- QDAC_CNTRL_REG (0X0B)
  54
- QDAC_STRB_REG (0X0C)
  56
- DEVICE_REG (0X0D)
  58
- I_Ddsinit_Reg(0X0E)
  60
- Q_Ddsinit_Reg(0X0F)
  62
- IPATTERN_REG (0X10)
  64
- QPATTERN_REG (0X11)
  66
- IPATTERN_REG2 (0X12)
  68
- QPATTERN_REG2 (0X13)
  70
- MEAS0_VAL_REG (0X14)
  72
- MEAS1_VAL_REG (0X15)
  74
- MEAS2_VAL_REG (0X16)
  76
- FREERUN_CNT_REG (0X17)
  78
- I_ARBWRITE_REG (0X18)
  80
- Q_ARBWRITE_REG (0X19)
  82
- ARB _CNTRL_REG (0X1A)
  84
- ARB _TICK_REG (0X1B)
  86
- AUXCNTRL_REG (0X1E)
  88
- PHASE_VALUE_REG (0X1F)
  90

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