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Summary of Contents for Alpha Data ADM-VPX3-9Z5-RTM
- Page 1 ADM-VPX3-9Z5-RTM User Manual Document Revision: 1.1 18th August 2022...
- Page 2 ADM-VPX3-9Z5-RTM User Manual V1.1 - 18th August 2022 © 2022 Copyright Alpha Data Parallel Systems Ltd. All rights reserved. This publication is protected by Copyright Law, with all rights reserved. No part of this publication may be reproduced, in any shape or form, without prior written consent from Alpha Data Parallel Systems Ltd.
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Page 3: Table Of Contents
Table 12 Header J15 ............................11 List of Figures Figure 1 ADM-VPX3-9Z5-RTM ........................1 Figure 2 ADM-VPX3-9Z5-RTM Block Diagram ....................4 Figure 3 ADM-VPX3-9Z5-RTM Top View ......................5 Figure 4 LED Locations ........................... 7 Figure 5 HS-MIO Configuration ........................8... - Page 4 ADM-VPX3-9Z5-RTM User Manual V1.1 - 18th August 2022 Page Intentionally left blank...
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Page 5: Introduction
V1.1 - 18th August 2022 1 Introduction The ADM-VPX3-9Z5-RTM is a 3U, VPX, Rear Transition Module (RTM) designed to interface with Alpha Data ADM-VPX3-9Z5 Zynq Ultrascale+ FPGA board. The ADM-VPX3-9Z5-RTM provides complete breakout of all backplane signals providing the user with complete flexibility during development and debug. -
Page 6: References & Specifications
ADM-VPX3-9Z5-RTM User Manual V1.1 - 18th August 2022 1.2 References & Specifications ANSI/VITA 46.0 VPX Baseline Standard, October 2007, VITA, ISBN 1-885731-44-2 ad_ug_1341 ADM-VPX3-9Z5 User Manual, June 2021, Alpha Data, - Table 1 : References Page 2 Introduction ad-ug-1392_v1_1.pdf... -
Page 7: Installation
ADM-VPX3-9Z5-RTM User Manual V1.1 - 18th August 2022 2 Installation 2.1 Software Installation Please refer to the ADM-VPX3-9Z5 area on the Alpha-Data support site for access to system monitoring utilities, documentation and FPGA reference designs. 2.2 Hardware Installation 2.2.1 Handling Instructions The components on this board can be damaged by electrostatic discharge (ESD). -
Page 8: Functional Description
ADM-VPX3-9Z5-RTM User Manual V1.1 - 18th August 2022 3 Functional Description 3.1 Block Diagram Figure 2 : ADM-VPX3-9Z5-RTM Block Diagram Page 4 Functional Description ad-ug-1392_v1_1.pdf... -
Page 9: Assembly Drawing
V1.1 - 18th August 2022 3.2 Assembly Drawing R100 C121 C107 C122 C108 C109 C110 C112 C111 C113 C104 C114 C115 C161 C130 C136 C153 C155 C157 C159 C154 C156 C158 C160 Figure 3 : ADM-VPX3-9Z5-RTM Top View Functional Description Page 5 ad-ug-1392_v1_1.pdf... -
Page 10: Connector Definitions
ADM-VPX3-9Z5-RTM User Manual V1.1 - 18th August 2022 3.3 Connector Definitions The description of the connectors on the board status shown below: Comp. Ref. Function NVMRO - not required on ADM-VPX3-9Z5 GPIO Enable. position 1-2 = GPIO Headers Disabled : 2-3 = Enabled... -
Page 11: Led Definitions
ADM-VPX3-9Z5-RTM User Manual V1.1 - 18th August 2022 3.4 LED Definitions The position and description of the board status LED is shown in Locations: D4 D5 Figure 4 : LED Locations Comp. Ref. Function ON State Off State D3(Green) Display Port 3.3V Supply Status... -
Page 12: Hs Mio Interfaces
V1.1 - 18th August 2022 3.6 HS MIO Interfaces The ADM-VPX3-9Z5-RTM allows support for the following PS GTR interfaces: displayport, ethernet and SATA. In order for the interfaces to be routed out correctly The PS GTR serial interfaces should be configured as... -
Page 13: Sata Connectors
V1.1 - 18th August 2022 3.9 SATA Connectors The ADM-VPX3-9Z5-RTM board has five standard right angle SATA receptacles for use with SATA compliant storage devices. One of the SATA devices is connected to the PS side and the remainder are connected to the PL side. -
Page 14: Rs232 Dtype
ADM-VPX3-9Z5-RTM User Manual V1.1 - 18th August 2022 3.12 RS232 Dtype Signal Name FPGA Pin PSMIO39 (P29) PSMIO38 (R27) Table 9 : Header J5 3.13 GPIO Headers Signal Name FPGA Pin P1_GP_1V8_P_10 AU11 P1_GP_1V8_P_9 AW11 P1_GP_1V8_N_10 AV11 P1_GP_1V8_N_9 AW10 GP4_1V8_P... -
Page 15: Table 11 Header J2
ADM-VPX3-9Z5-RTM User Manual V1.1 - 18th August 2022 Signal Name FPGA Pin P1_GP_1V8_P_12 P1_GP_1V8_P_11 AV12 P1_GP_1V8_N_12 P1_GP_1V8_N_11 AW12 GP8_1V8_P AM11 GP7_1V8_P AM10 GP8_1V8_N AN11 GP7_1V8_N AN10 GP6_1V8_P AL15 GP5_1V8_P AL14 GP6_1V8_N AM15 GP5_1V8_N AM14 Table 11 : Header J2 Signal Name... - Page 16 ADM-VPX3-9Z5-RTM User Manual V1.1 - 18th August 2022 Revision History Date Revision Nature of Change Initial Release 08 June 2021 Added extra detail to tables 18 August 2022 Address: Suite L4A, 160 Dundee Street, Address: 10822 West Toller Drive, Suite 250...
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