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Alpha Data XRM-IO146 I/O Interface Connector for ADM-XRC-5T1 Image/ Video Processing Module In Stock Used and in Excellent Condition Open Web Page https://www.artisantg.com/63354-1 A l l t r a d e m a r k s , b r a n d n a m e s , a n d b r a n d s a p p e a r i n g h e r e i n a r e t h e p r o p e r t y o f t h e i r r e s p e c t i v e o w n e r s .
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ADM-XRC-5T1 User Manual Revision: 2.2 Date: 2nd April 2012...
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All rights reserved. This publication is protected by Copyright Law, with all rights reserved. No part of this publication may be reproduced, in any shape or form, without prior written consent from Alpha Data Parallel Systems Limited. Head Office US Office...
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2.2 Motherboard / Carrier requirements ......................... 2 2.3 PCI Mode selection ............................2 2.4 Installing the ADM-XRC-5T1 onto a PMC motherboard................... 2 2.5 Installing the ADM-XRC-5T1 if fitted to an ADC-PMC ..................2 2.6 Cooling Requirements............................3 3 Software Installation ............................4 4 Board Description ...............................
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(v2.2 - 2nd April 2012) 1 Introduction The ADM-XRC-5T1 is a high performance PCI Mezzanine Card (PMC) designed for applications using the Virtex™-5 FPGAs from Xilinx. This card supports VIrtex-5 LX110T, LX155T, SX95T and FX70T devices with the FFG1136 package.
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The ADM-XRC-5T1 is a 3.3V only PCI device and is not compatible with systems that use 5V signalling. The ADM-XRC-5T1 must be installed in a PMC motherboard or carrier that supplies +5.0V and +3.3V power to the PMC connectors. Ensure that this requirement is satisfied before powering it up. +12V and -12V may also be required for certain XRM modules.
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(v2.2 - 2nd April 2012) It should be noted that the ADC-PMC uses a standard bridge to provide a secondary PCI bus for the ADM-XRC-5T1 and that some older BIOS code does not set up these devices correctly. Please ensure you have the latest version of BIOS appropriate for your machine.
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(v2.2 - 2nd April 2012) 3 Software Installation Please refer to the SDK installation CD. The SDK contains drivers, examples for host control and FPGA design and comprehensive help on application interfacing. Page 4 Software Installation Alpha Data Parallel Systems Ltd. ad_ug01159...
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(v2.2 - 2nd April 2012) 4 Board Description The ADM-XRC-5T1 follows the architecture of the ADM-XRC series and decouples the "target" FPGA from the PCI interface, allowing user applications to be designed with minimum effort and without the complexity of PCI design.
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4.2 Local Bus The ADM-XRC-5T1 implements a multi-master local bus between the bridge and the target FPGA using a 32- or 64-bit multiplexed address / data path. The bridge design is asynchronous and allows the local bus to be run faster or slower than the PCI bus clock to suit the requirements of the user design.
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ADM-XRC-5T1 User Manual (v2.2 - 2nd April 2012) 4.3 Flash Memory The ADM-XRC-5T1 is fitted with two separate Flash memories: one connected to the Bridge / Control FPGA and the other to the User FPGA. 4.3.1 Board Control Flash A 256Mb Flash memory (Intel / Numonyx PC28F256P30) is used for storing Vital Product Data (VPD), programmable clock parameters and configuration bitstreams for the User FPGA.
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4.4 Health Monitoring The ADM-XRC-5T1 has the ability to monitor temperature and voltage to maintain a check on the operation of the board. The monitoring is implemented by a National Semiconductor LM87 and is supported by the Bridge FPGA control logic using I2C.
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+3V3 Reading = 3.32 V +5V Reading = 5.04 V Pn4 Reading = 3.31 V FPIO Reading = 3.34 V SysMon Int Temp = 33 deg. C User FPGA Temp = 26 deg. C Board Description Page 9 ad_ug01159 Alpha Data Parallel Systems Ltd.
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SCAN chain is initialised. The JTAG Header pinout is shown in Figure 6, "JTAG Header J2": Figure 6: JTAG Header J2 The scan chain is shown in Figure 7, "JTAG Boundary Scan Chain": Page 10 Board Description Alpha Data Parallel Systems Ltd. ad_ug01159...
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FPGA if one is present. Shorting FBS to the adjacent GND pin will disable this process and can be used to recover situations where rogue bitstreams have been stored in flash. Board Description Page 11 ad_ug01159 Alpha Data Parallel Systems Ltd.
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ADM-XRC-5T1 User Manual (v2.2 - 2nd April 2012) 4.6 Clocks The ADM-XRC-5T1 is provided with numerous clock sources, as shown in Figure 8, "Clock Structure" below: RefClk PCI-X Zero-delay Buffer Bridge Config (PLL) (Coolrunner) Bridge FPGA (V4LX25) XTAL_CLK REFCLK_200M 25.0 MHz...
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In order to make use of the IODELAY features of Virtex™-5, a stable low-jitter clock source is required to provide the base timing for tap delay lines in each IOB in the User FPGA. The ADM-XRC-5T1 is fitted with a 200MHz LVPECL (LVDS optional) oscillator connected to global clock resource pins.
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80MB/s. The ADM-XRC-5T1 can be configured to boot the User FPGA from flash on power-up if a valid bit-stream is detected in the flash. Booting from flash will also configure the programmable clocks. See Section 4.3.1.1, "Power-Up Sequence"...
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4.7.3 Memory Interfaces 4.7.3.1 DDRII SDRAM The ADM-XRC-5T1 has two independent banks of DDRII SDRAM. Each bank consists of two memory devices in parallel to provide a 32 bit datapath. 1Gb Micron MT47H64M16-3 devices are fitted as standard to provide 256MB per bank. The board supports 2Gb devices and these are available as an ordering option.
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The signalling voltage on the XRM connector (and User FPGA Banks 12, 18, 20 & 22) is selectable by jumper J3. XRM I/O voltage Link p1 & p2 3.3V Link p2 & p3 2.5V Link p3 & p4 2.5V Link p5 & p4 1.8V Table 8: XRM I/O Voltage Selection Page 16 Board Description Alpha Data Parallel Systems Ltd. ad_ug01159...
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It should be noted that the switch does not directly route power. The switch position is monitored by the board control logic which, in turn, sets a power multiplexer to use either 2.5V or 3.3V. Page 22 Board Description Alpha Data Parallel Systems Ltd. ad_ug01159...
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