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Summary of Contents for SEA 245
- Page 1 SEA INC OF DELAWARE PRELIMINARY MAINTENANCE MANUAL EXCERPTS ON THEORY OF OPERATION MF/HF SSB GMDSS RADIOTELEPHONE/DSC CONTROLLER MODEL SEA 245 (c) Copyright 2001 SEA, Inc. All rights reserved. SEA, Inc. 7030 220th St. S.W. Mountlake Terrace, Washington 98043 (425) 771-2182...
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Page 2: Table Of Contents
THE 2187.5 MONITOR RECEIVER ...................... 5-14 THE POWER SUPPLY CIRCUIT ........................5-17 THE MAINBOARD CONTROLLER AND DSP PROCESSORS ..............5-20 THE SEA 245 FRONT PANEL/CONTROLLER SYSTEM ................6-1 GENERAL ................................6-1 THEORY OF OPERATION ..........................6-1 LIST OF FIGURES 5.2.1 RECEIVER BLOCK DIAGRAM ........................5-2 5.3.1 TRANSMITTER BLOCK DIAGRAM ...................... -
Page 3: Theory Of Operation
I/Q modulator, together with an appropriate DSP algorithm to generate the desired baseband signal at 45 MHz. The frequency control circuitry in the SEA 245 uses a combination of two PLL- based frequency synthesizers and the system DSP engine to provide the various frequency conversions. -
Page 4: Receiver Block Diagram
SEA 245 Receiver Block Diagram Figure 5.2.1... - Page 5 5.2.1 BLOCK DIAGRAM Figure 5.2.1 shows the block diagram of the receive mode. The received RF signal is routed from the rear panel antenna jack to a low pass filter selected by a relay bank on the PA/Filter Assembly (ASY-0245-02). The output of the filter is routed from J4 on the PA/Filter Assembly through a coaxial cable to the receiver input circuitry on the Mainboard Assembly (ASY-0245-01).
- Page 6 A/D converter that moves the signal from the analog to the digital realm. In the SEA 245, A/D Converter U34 is a 24-bit, 96 kHz stereo ADC with a dynamic range of 110 dB and greater than 100 dB signal-to-noise ratio. The inputs to the ADC are full differential and the chip includes a reference filter and a digital decimation filter, which minimizes requirements for anti-aliasing filtering.
- Page 7 Assembly. 5.2.7 THE DIGITAL SIGNAL PROCESSOR The main DSP engine in the SEA 245 consists of U7 on the CPU Board Assembly. This is a TMS320VC5402, a specialized type of microprocessor which includes such features as a 40-bit ALU, data bus with Bus-Holder feature, extended...
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Page 8: Transmitter Block Diagram
SEA 245 Transmitter Block Diagram Figure 5.3.1... -
Page 9: The Transmitter
THE TRANSMITTER 5.3.1 BLOCK DIAGRAM Figure 5.3.1 shows the block diagram of the SEA 245 in the transmit mode. Microphone audio is amplified and converted to a balanced format for transmission from the Front Panel/Controller Assembly to the Mainboard Assembly (ASY-0245- 01) via the SEAbuss audio lines. - Page 10 consisting of operational amplifiers U10C and U10D. MOSFET Q5 is connected between the junction of R94 and C13X and ground and serves to mute the microphone circuitry in the receive mode. The balanced audio output from U10C and U10D passes through analog gates U13A and U13D to the SEAbuss audio line. The SEABUSS audio interconnection between the Front Panel/Controller Assembly (ASY-0245-03) and the Mainboard Assembly (ASY-0245-01) is through the 8-pin ribbon cable between P2 on the Controller board and J4 on the Mainboard.
- Page 11 MHz LO and produces two 45.016 MHz LO signals with a 90 degree phase differential. These are used as the two local oscillators for the mixers. One is mixed with the I component and the other is mixed with the Q component. The two mixer outputs are summed to complete the single sideband mixer.
- Page 12 +12VTX rail. 5.3.10 THE TRANSMITTER POWER AMPLIFIER The power amplifier in the SEA 245 is a push-pull common emitter design with a temperature stabilized bias source. The amplifier runs from the +24 volt input and has the collector voltage present at all times. The amplifier is activated by turning on the various bias supplies when in the transmit mode.
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Page 13: The Master Clock Oscillator And Synthesizer System
THE MASTER CLOCK OSCILLATOR AND SYNTHESIZER SYSTEM 5.4.1 BLOCK DIAGRAM Figure 5.4.1 shows the block diagram of the local oscillator system of the SEA 245. The block diagram illustrates a total of two synthesizers. The first local oscillator operates from 45 to 75 MHz and uses three bandswitched VCOs. These are controlled by synthesizer chip, U21, which contains a dual modulus divide-by-N counter, a variable modulus reference counter and a phase detector. - Page 14 Switch transistors Q16, Q17 and Q18 provide power to the selected VCO. The base of Q18 is pulled low through R146 supplying 10 volts to the HIGHBAND VCO, Q23-Q24. When the MIDBAND VCO is selected, Q13 will be turned on by a high on pin 16 of U21.
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Page 15: Synthesizer Block Diagram
SEA 245 Synthesizer Block Diagram Figure 5.4.1 5-13... -
Page 16: The 2187.5 Khz Monitor Receiver
The first IF frequency is 455 kHz, the second IF frequency is nominally 14.583 kHz. As in the SEA 245 Main Receiver, the DSP engine provides all channel selectivity, signal demodulation, and AGC. -
Page 17: 2187.5 Khz Monitor Block Diagram
SEA 245 2187.5 KHz MONITOR BLOCK DIAGRAM Figure 5.5.1 5-15... - Page 18 The first mixer is a conventional +7 dBm double balanced type, which provides excellent dynamic range in this application. 5.5.3 THE 455 kHz IF AMPLIFIER The first 455 kHz IF amplifier is Q10, a grounded-gate JFET which provides some gain and serves as a wideband 50 ohm termination for the mixer. The output from the amplifier is passed through FL3, a 6-pole ceramic bandpass filter with a nominal bandwidth of 4 kHz.
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Page 19: The Power Supply Circuit
24/12 volt DC/DC converter which provides the regulated, chassis referenced, +12 volt rail. The +12 volt rail powers the low level circuitry in the SEA 245. Each fuse is individually protected from reverse polarity by power diodes CR1 and CR2 and each power rail is individually filtered by 470 μF capacitors C29 and C47. -
Page 20: Power Distribution Block Diagram
BIAS CONTROL -12VSW Q2,Q3 CHASSIS +12VSW +12VSW Q1,Q4,Q5 F3,5A +12TX(PA) ON/OFF PA/FILTER (ASY-0245-02) CHASSIS ASY-0245-03 +10VTX +12VSW TXINT +10VTX TXEN RXEN 12VSW MAINBOARD (ASY-0245-01) CHASSIS +10V +12VRX +3.3V +5VAD +12TX 12VSW SEA 245 Power Distribution Block Diagram Figure 5.6.1 5-18... - Page 21 5.6.4 +10 VOLT REGULATOR AND THE +10VTX SWITCH The internal +10V rails are derived from the +12VSW buss through regulator U38. The +10VTX rail is generated by inverted switch Q27. Grounding the notTXEN line will turn on Q27, enabling the +10VTX rail. The notTXEN line comes from the PA/Filter Assembly through pin 9 of J6.
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Page 22: The Mainboard Controller And Dsp Processors
circuitry. 5.6.9 THE +24VTX RAIL AND PA BIAS SYSTEM Bias for the PA output transistors is generated from the +24VTX rail. Since the entire +24 volt power source is isolated from the chassis, an optical isolator, U5 on the PA/Filter Assembly (ASY-0245-02) is used to switch on a P-channel FET (Q12) when the +12VTX rail is energized. - Page 23 SEA 245 Processor Assembly Block Diagram Figure 5.7.1 5-21...
- Page 24 5.7.4 MICROCONTROLLER OPERATION Reset generator, U8 provides a reset pulse to microcontroller U5 at startup or if there is a dip in the power supply. At startup the microcontroller has access only to the internal resources. It runs software contained in the internal EEPROM. This software configures the chip and either boots a program from the RS-232 port (Useful for service and reprogramming functions) or transfers control to the flash memory.
- Page 25 samples are processed to convert them to the audio band, filter out undesired signals and provide gain control and noise blanking. Watch Receiver signals are also FSK demodulated in order to detect Digital Selective Calling (DSC) data. Audio samples from the Main Receiver are passed to the speaker audio circuit through the CODEC monophonic output.
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Page 26: The Sea 245 Front Panel/Controller System
SEA 245 as well as in remote installations. The SEA 245 will support a SINGLE remote controller and a SEABUSS compatible Antenna Tuner such as the SEA 1631. - Page 27 SEA 245 Mainboard Assembly through buffer amplifier Q7. 6.2.1 KEYBOARD SUPPORT The SEA 245/SEA 2450 keyboard has a total of 19 keys. Key status is determined by scanning the matrix through control lines from the CPU chip, U1. 6.2.2 THE LCD DISPLAY AND DISPLAY LIGHTING DISPLAY: The front panel display is a LED backlighted LCD graphic module.
- Page 28 This means that when the SEA 2450 Remote Controller is used, the status of the SEA 245 is reflected at both operating stations. Controller-SEA 245 data is sent in packets and is error checked. Collision protection is provided for all data sources.
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