Machine Trap Vector (Mtvec) - SiFive E31 Manual

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5.3.5 Machine Trap Vector (
By default, all interrupts trap to a single address defined in the
interrupt handler to read
support the ability to optionally enable interrupt vectors. When vectoring is enabled, each inter-
rupt defined in will trap to its own specific interrupt handler. This allows all local interrupts to
mie
trap to exclusive handlers. Even with vectoring enabled, all global interrupts will trap to the same
global interrupt vector.
Vectored interrupts are enabled when the MODE field of the
CSR
Bits Field Name
[1:0]
[31:2] BASE[31:2]
Value
0
1
≥ 2
If vectored interrupts are disabled (
address. If vectored interrupts are enabled (
+ 4 × exception code. For example, if a machine timer interrupt is taken, the
mtvec.BASE
set to + 0x1C. Typically, the trap vector table is populated with jump instructions to
mtvec.BASE
transfer control to interrupt-specific trap handlers.
In vectored interrupt mode, BASE must be 128-byte aligned.
All machine external interrupts (global interrupts) are mapped to exception code of 11. Thus,
when interrupt vectoring is enabled, the
interrupt.
See Table 10 for a description of the
field. See Table 9 for the E31 Core Complex interrupt exception code values.
mtvec.MODE
)
mtvec
and react accordingly. RISC‑V and the E31 Core Complex also
mcause
Machine Trap Vector Register
Attr.
MODE WARL
WARL
Table 10:
MODE Field Encoding
Name
Direct
Vectored
Reserved
Table 11: Encoding of
mtvec.MODE
pc
mtvec
mtvec
mtvec
Description
determines whether or not interrupt
MODE
vectoring is enabled. The encoding for the
field is described in Table 11.
MODE
Interrupt Vector Base Address. Must be
aligned on a 128-byte boundary when
MODE=1. Note, BASE[1:0] is not present in
this register and is implicitly 0.
Register
mtvec
mtvec.MODE
Description
All exceptions set
pc
Asynchronous interrupts set
cause.
mtvec.MODE
=0), all interrupts trap to the
=1), interrupts set the
mtvec.MODE
is set to address
mtvec.BASE
register. See Table 11 for a description of the
register. It is up to the
mtvec
register is set to 1.
to
BASE
to + 4 ×
pc BASE
mtvec.BASE
to
pc
+ 0x2C for any global
20
is
pc