Stack Pointer (Sp); Format Of Stack Pointer - NEC 78K/0S Series User Manual

(1) Interrupt enable flag (IE)
This flag controls interrupt request acknowledge operations of the CPU.
When IE = 0, all interrupts except non-maskable interrupts are disabled (DI status).
When IE = 1, interrupts are enabled (EI status). At this time, acknowledgment of interrupt requests is
controlled by the interrupt mask flag for each interrupt source.
The IE flag is reset (0) when the DI instruction execution is executed or when an interrupt is acknowledged,
and set (1) when the EI instruction is executed.
(2) Zero flag (Z)
When the operation result is zero, this flag is set (1); otherwise, it is reset (0).
(3) Auxiliary carry flag (AC)
If the operation result has a carry from bit 3 or a borrow to bit 3, this flag is set (1); otherwise, it is reset (0).
(4) Carry flag (CY)
This flag records an overflow or underflow upon add/subtract instruction execution. It also records the shift-
out value upon rotate instruction execution, and functions as a bit accumulator during bit operation instruction
execution.

2.1.3 Stack pointer (SP)

This is a 16-bit register that holds the first address of the stack area in the memory. Only the internal high-speed
RAM area can be set as the stack area.
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SP SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0
The SP is decremented ahead of write (save) to the stack memory, and is incremented after read (reset) from the
stack memory.
The data saved/restored as a result of each stack operation are as shown in Figures 2-4 and 2-5.
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Caution Since RESET input makes the SP contents undefined, be sure to initialize the SP before
executing an instruction.
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CHAPTER 2 REGISTERS
Figure 2-3. Format of Stack Pointer
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