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Scan Control
Register
base + 06
15
14
16
Write
Read
Clear Scan List
(CLR SCN)
Digital Bus Enable
(DBS EN)
Immediate Enable
(IMM EN)
Continuous Enable
(CNT EN)
Reset Pointer
(RST PTR)
Scan Channel
Delay Register
base + 08
15
14
16
Write
Read
D3 - D0
88 HP E1351A/53A Register-Based Programming
The Scan Control Register allows you to clear the scan list, set the trigger
mode and reset the pointer to the beginning of the scan list. This register is
a READ-back register, allowing you to verify the state of the WRITE
register.
13
12
11
10
Undefined
Undefined
Writing a one (1) in this bit clears the scan list. The bit must be set back to
zero (0) after flushing. CLR SCN (Read) returns the state of the bit.
Writing a one (1) enables the digital bus trigger mode. A zero (0) disables
it. DBS EN (Read) returns the state of the bit.
Writing a one (1) in this bit sets trigger to immediate, which means that as
soon as the first channel is closed by the TRG INT, the entire scan list is run
without any further triggering. Channel advance speed is determined by the
delay time specified. This has extremely limited applications.
Writing a one (1) in this bit enables the card to continually cycle through the
scan list. When this bit is enabled, the last channel in a scan list resets the
pointer back to the beginning of the scan list.
Writing a one (1) resets the pointer back to the beginning of the scan list.
CNT EN true automatically resets pointer at end of scan list. If CNT EN is
set true, an interrupt also resets the pointer. If CNT EN is set false, the last
channel in the scan list generates an interrupt if the channel is valid (VLD*
set true).
The Scan Channel Delay Register sets the
receipt of a channel closing trigger and the Channel Closed pulse. The
n
µ
delay is 2
S and
least significant bit. This register is a read-back register, allowing you to
verify the state of the WRITE register.
13
12
11
10
Undefined
Undefined
D0 is the least significant bit, D3 is the most significant. These bits
designate a number between 0 and 15 for
9
8
7
6
X
X
1
1
n
has a range of 0 to 15. D3 to D0 set
9
8
7
6
X
X
1
1
n
5
4
3
2
X
RST
CNT
IMM
DBS
PTR
EN
EN
1
1
CNT
IMM
DBS
EN
EN
, the time between
SETTling:TIME
n
, and D0 is the
5
4
3
2
X
X
D3
D2
1
1
D3
D2
.
Appendix B
1
0
CLR
EN
SCN
CLR
EN
SCN
1
0
D1
D0
D1
D0
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