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Service Information
IDDATA
(Data output
from mainframe
or ROM)
IDDATA
(Data output
from mainframe
or ROM)
Figure 5-9
Transmit and acknowledge sequence
5.5.4 Relay power control
A relay power control circuit, made up of U106, U107,
Q100, Q101, and associated components, keeps power
dissipated in relay coils at a minimum, thus reducing
possible problems caused by thermal EMFs.
During steady-state operation, the relay supply volt-
age, +V, is regulated to +3.5V to minimize coil power
dissipation. When a relay is first closed, the STROBE
pulse applied to U106 changes the parameters of the
relay supply voltage regulator, Q100, allowing the
relay supply voltage, +V, to rise to +5.7V for about
100ms. This brief voltage rise ensures that relays close
as quickly as possible. After the 100ms period has
elapsed, the relay supply voltage (+V) drops back
down to its nominal steady-state value of +3.5V.
5.5.5 Power-on safeguard
The
power-on
discussed in the following paragraph
is actually located on the digital board
in the Model 7001 mainframe.
5-14
ID CLK
Start
NOTE
safeguard
circuit
1
8
A power-on safeguard circuit, made up of U114 (a
D-type flip-flop) and associated components ensures
that relays do not randomly energize on power-up and
power-down. This circuit disables all relays (all relays
are open) during power-up and power-down periods.
The PRESET line on the D-type flip-flop is controlled
by the 68302 microprocessor, while the CLK line of the
D-type flip-flop is controlled by a port line on the 68302
processor. The Q output of the flip-flop drives each
switch card relay driver IC enable pin (U100-U104,
pin 8).
When the 68302 microprocessor is in the reset mode,
the flip-flop PRESET line is held low, and Q out imme-
diately goes high, disabling all relays (relay driver IC
enable pins are high, disabling the relays.) After the
reset condition elapses ( ≈ 200msec), PRESET goes high
while Q out stays high. When the first valid STROBE
pulse occurs, a low logic level is clocked into the D-
type flip-flop, setting Q out low and enabling all relay
drivers simultaneously. Note that Q out stays low,
(enabling relay drivers) until the 68302 processor goes
into a reset condition.
9
Acknowledge
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