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e2v TSEV81102G0FS User Manual

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TSEV81102G0FS Evaluation Board
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User Guide

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Summary of Contents for e2v TSEV81102G0FS

  • Page 1 TSEV81102G0FS Evaluation Board ....................User Guide...

  • Page 3: Table Of Contents

    DMUX Function Settings................2-6 Layout Information ..................2-6 2.7.1 Decoupling of Power Supplies............2-6 2.7.2 Reference Planes ................2-6 2.7.3 I/O Transmission Lines...............2-7 Section 3 Operating Characteristics ..............3-1 Output Characteristics ................3-1 Electrical Characteristics................3-2 TSEV81102G0FS Evaluation Board User Guide 0974C–BDC–02/09 e2v semiconductors SAS 2009...
  • Page 4 Procedure ...................4-1 Adjustments to DMUX Setting ..............4-2 BIST ......................4-3 Delay Adjust Function ................4-3 Die Junction Temperature Monitoring ............4-4 Applying the TSEV81102G0FS DMUX to e2v ADC Evaluation Boards ...4-4 Miscellaneous ...................4-5 Section 5 Package Description................5-1 Pin Description ..................5-1 Enhanced CQFP 196 Pinout..............5-3 CQFP 196 Outline Dimensions ..............5-4...

  • Page 5: Introduction

    Output data common mode and swing adjustment Die junction temperature measurements over military temperature range The DMUX EB is designed to enable easy connection to e2v’s ADC Evaluation Boards (for example, TSEV8388BGL and TSEV83102G0BGL) for an extended functionality evaluation (ADC and DMUX multi-channel applications).
  • Page 6 Introduction TSEV81102G0FS Evaluation Board User Guide 0974C–BDC–02/09 e2v semiconductors SAS 2009...

  • Page 7: Hardware Description

    CQFP package are mirror images of the ones on the DMUX in a TBGA 240 package. This results in having to flip the DMUX board over to make it compatible with other e2v ADC boards (such as the TSEV8388Bxx or TSEV83102G0BXX ADC evaluation boards).
  • Page 8 Dx/Dxb Ix/Ixb DMUX Evaluation Board Component Side ADC Evaluation Board Component Side Figure 2-3. TSEV81102G0FS Board Simplified Cross Section (Board Mounting for Compatibility with TSEV8388GL/GLZA2 and TSEV83102G0BGL ADC Boards) Heatsink mounted on the bottom side of the CQFP 196 Signal Layer CQFP 196 DMUX Figure 2-4.
  • Page 9 Hardware Description Figure 2-5. TSEV81102G0FS Evaluation Board Block Diagram BANANA JACKS (4mm) BANANA SUBVIS JACKS Connectors PORT A Connector PITCH CONNECTORS (2 mm) (2.54 mm) IGND Power Supplies PORT C IDIODE VDIODE DMUX DelAdj VGND PORT E Sync Reset (Diff.)

  • Page 10: Board Structure

    2.5 GHz), which has an enhanced dielectric consistency in the high frequency domain, and is dedicated to the routing of 50Ω and 60Ω traces. The RO4003 dielectric constant is typically 3.4 at 10 GHz. TSEV81102G0FS Evaluation Board User Guide 0974C–BDC–02/09 e2v semiconductors SAS 2009...

  • Page 11: Power Supplies And Ground Access

    2.4.4 Access to the differential signal ADCDelAdjln/ADCDelAdjlnb is provided by two SMA Synchronization connectors via 50Ω microstrip lines. Input Signal Access Note: 100Ω differential impedance matching is performed on-chip. TSEV81102G0FS Evaluation Board User Guide 0974C–BDC–02/09...

  • Page 12: Output Access

    Each reference plane (layers 3 and 7) is physically divided into two parts: one GND plane and one V plane, which is the voltage reference for the output buffers of the PLUSD TSEV81102G0FS Evaluation Board User Guide 0974C–BDC–02/09 e2v semiconductors SAS 2009...

  • Page 13: I/O Transmission Lines

    DRDRb Differential 60Ω 50Ω 113.5 mm SyncResetSync On-chip 100Ω Differential 85.7 mm ±1 50Ω Resetb differential ADCDelAdjInAD On-chip 100Ω Differential 100 mm ±1 50Ω CDelAdjInb differential ADCDelAdjOut Differential 106 mm ±1 50Ω None ADCDelAdjOutb TSEV81102G0FS Evaluation Board User Guide 0974C–BDC–02/09...
  • Page 14 Hardware Description TSEV81102G0FS Evaluation Board User Guide 0974C–BDC–02/09 e2v semiconductors SAS 2009...

  • Page 15: Operating Characteristics

    Table 3-1. Examples of Output Buffer Format Settings Parameter PECL Unit PLUSD –2 Swing ±0.5 ±0.5 ±1 Reference –1.58 1.72 1.28 –1.02 2.28 2.28 –1.99 1.31 0.28 Load >75 Average output current TSEV81102G0FS Evaluation Board User Guide 0974C–BDC–02/09 e2v semiconductors SAS 2009...

  • Page 16: Electrical Characteristics

    °C Note: Absolute maximum ratings are limiting values, to be applied individualy, while other parameters are within specified operating conditions. Long exposure to maximum ratings may affect device long-term reliability. TSEV81102G0FS Evaluation Board User Guide 0974C–BDC–02/09 e2v semiconductors SAS 2009...

  • Page 17: Operating Characteristics

    0 < T < 90 Operating junction Industrial grade “V” –40 < T < 110 °C temperature Military grade “M” –55 < T < 125 Operating Please refer to the “TS81102G0FS DMUX” specification. Characteristics TSEV81102G0FS Evaluation Board User Guide 0974C–BDC–02/09...
  • Page 18 Operating Characteristics TSEV81102G0FS Evaluation Board User Guide 0974C–BDC–02/09 e2v semiconductors SAS 2009...

  • Page 19: Application Information

    Then connect the supply's ground to – GND. 6. Connect a signal generator to the DMUX CLKIN and CLKINB clock input pitches. The DMUX input clock can be either differential or single-ended. TSEV81102G0FS Evaluation Board User Guide 0974C–BDC–02/09 e2v semiconductors SAS 2009...

  • Page 20: Adjustments To Dmux Setting

    DMUX settings for the RATIOSEL, NBBIT, BIST and CLKINTYPE jumper positions. Table 4-1. DMUX Setting Adjustments Name Jumper Function DR/2 mode CLKINTYPE DR mode BIST active BIST BIST inactive 8-bit mode NBBIT 10-bit mode 1:8 ratio RATIOSEL 1:4 ratio TSEV81102G0FS Evaluation Board User Guide 0974C–BDC–02/09 e2v semiconductors SAS 2009...

  • Page 21: Bist

    The input signal DelAdjCtrl is tied to GND. The input signal DelAdjCtrlb can vary from -0.55V to 0.55V, depending on the potentiometer position. The generated delay is proportional to the differential across DelAdjCtrl and TSEV81102G0FS Evaluation Board User Guide 0974C–BDC–02/09...

  • Page 22: Die Junction Temperature Monitoring

    When it is used with the TSEV8388BGL/GLZA2 or TSEV83102G0BGL ADC boards, the TSEV81102G0FS DMUX board must be turned over, with the device on the bottom of the board and I0 matched with D0 of the ADC board. TSEV81102G0FS Evaluation Board User Guide 0974C–BDC–02/09...

  • Page 23: Miscellaneous

    (ESD). Make sure the current delivered by the power supply is sufficient to supply the board. Always switch on the DMUX board supplies in the following order: V first, V and VTT. PLUSD TSEV81102G0FS Evaluation Board User Guide 0974C–BDC–02/09...
  • Page 24 After the supplies are switched on, send an asynchronous reset pulse into the DMUX (i.e. leave the pad ASYNCRESET open and then connect it to ground) in order to start the device. TSEV81102G0FS Evaluation Board User Guide 0974C–BDC–02/09 e2v semiconductors SAS 2009...

  • Page 25: Package Description

    9, 12, 15, 18, 24, 27, 30, 33, 36, 39 In-phase input data I[0…9]B 8, 11, 14, 17, 23, 26, 29, 32, 35, 38 Inverted phase input data SyncReset In-phase synchronous reset SyncResetB Inverted phase synchronous reset TSEV81102G0FS Evaluation Board User Guide 0974C–BDC–02/09 e2v semiconductors SAS 2009...
  • Page 26 Asynchronous reset (active high) BIST Built-in self-test mode (active low) Other Output Signals ADCDelAdjOUT In-phase output of the stand-alone delay cell ADCDelAdjOUTB Inverted phase output of the stand-alone delay cell TSEV81102G0FS Evaluation Board User Guide 0974C–BDC–02/09 e2v semiconductors SAS 2009...

  • Page 27: Enhanced Cqfp 196 Pinout

    Package Description Enhanced CQFP 196 Pinout Figure 5-1. CQFP 196 Package Pinout Top View TSEV81102G0FS Evaluation Board User Guide 0974C–BDC–02/09...

  • Page 28: Cqfp 196 Outline Dimensions

    Figure 5-2. CQFP 196 Package Top View Lands for Capacitor (Chip size 0603) Chamfer 0.5 ±0.25 Chamfer 0.76 ±0.25 (x3) Pin 1 Index 18.54 mm 33.91 mm ±0.10 mm 38.80 mm ±0.18 mm TSEV81102G0FS Evaluation Board User Guide 0974C–BDC–02/09 e2v semiconductors SAS 2009...
  • Page 29 Leads Board at Bottom Board at Bottom of Package of Leads Thermal Resistance Junction to bottom of case = 0.26 + 0.31 + 1.44 + 0.07 + 0.07 = 2.15˚C/Watt (customer thermal interface excluded) TSEV81102G0FS Evaluation Board User Guide 0974C–BDC–02/09...
  • Page 30 Package Description TSEV81102G0FS Evaluation Board User Guide 0974C–BDC–02/09 e2v semiconductors SAS 2009...

  • Page 31: Ordering Information

    Contact e2v sales –55°C < Tc; Tj < 125°C “M” grade TS81102G0MFS9NB1 CQFP 196 ESA/SCC Contact e2v sales –55°C < Tc; Tj < 125°C TSEV81102G0FS CQFP 196 Ambient Prototype Contact e2v sales TSEV81102G0FS Evaluation Board User Guide 0974C–BDC–02/09 e2v semiconductors SAS 2009...
  • Page 32 Ordering Information TSEV81102G0FS Evaluation Board User Guide 0974C–BDC–02/09 e2v semiconductors SAS 2009...

  • Page 33: Appendices

    Section 7 Appendices TSEV81102G0FS Evaluation Board User Guide 0974C–BDC–02/09 e2v semiconductors SAS 2009...

  • Page 34: Electrical Schematics

    Electrical Schematics Figure 7-1. TSEV81102G0FS Electrical Schematics TSEV81102G0FS Evaluation Board User Guide 0974C–BDC–02/09 e2v semiconductors SAS 2009...
  • Page 35 Figure 7-2. TSEV81102G0FS Component Layer (Top) Figure 7-3. TSEV81102G0FS Component Layer (Bottom) TSEV81102G0FS Evaluation Board User Guide 0974C–BDC–02/09...
  • Page 36 Figure 7-4. TSEV81102G0FS Top Layer Figure 7-5. TSEV81102G0FS Second Layer (GND and V PLUSD TSEV81102G0FS Evaluation Board User Guide 0974C–BDC–02/09 e2v semiconductors SAS 2009...
  • Page 37 Figure 7-6. TSEV81102G0FS Third Layer (GND and Power Supplies) Figure 7-7. TSEV81102G0FS Fourth Layer (GND, V and Miscellaneous) PLUSD TSEV81102G0FS Evaluation Board User Guide 0974C–BDC–02/09...
  • Page 38 TSEV81102G0FS Evaluation Board User Guide 0974C–BDC–02/09 e2v semiconductors SAS 2009...
  • Page 39 Whilst e2v has taken care to ensure the accuracy of the information contained herein it accepts no responsibility for the consequences of any use thereof and also reserves the right to change the specification of goods without notice. e2v accepts no liability beyond that set out in its standard conditions of sale in respect of infringement of third party patents arising from the use of tubes or other devices in accordance with information contained herein.

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