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e2v TSEV8308500 User Manual

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TSEV8308500 Evaluation Board
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User Guide

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Summary of Contents for e2v TSEV8308500

  • Page 1 TSEV8308500 Evaluation Board ....................User Guide...

  • Page 3: Table Of Contents

    Setting the Digital Output Data Format .............4-1 ADC Gain Adjust..................4-2 SMA Connectors and Microstrip Lines De-embedding Fixture ....4-2 Temperature Monitoring and Data Ready Reset Function .......4-3 Data Ready Output Signal Reset ..............4-4 TSEV8308500 Evaluation Board User Guide 0968D–BDC–01/09 e2v semiconductors SAS 2009...
  • Page 4 Test Bench Description ................4-5 Section 5 Package Description................5-1 TS8308500GL Pinout ................5-1 Thermal Characteristics ................5-3 Section 6 Schematics ................... 6-1 TSEV8308500 Electrical Schematics ............6-1 Evaluation Board Schematics ..............6-4 TSEV8308500 Evaluation Board User Guide 0968D–BDC–01/09 e2v semiconductors SAS 2009...

  • Page 5: Overview

    Overview Description The TSEV8308500 Evaluation Board (EB) is a prototype board which has been designed in order to facilitate the evaluation and the characterization of the TS8308500 device up to its 1.3 GHz full analog power bandwidth at up to 500 Msps in the extended temperature range.

  • Page 6: Evaluation Board

    Overview TSEV8308500 Evaluation Board Figure 1-1. TSEV8308500 Block Diagram Z0 = 50 Differential Clock inputs Z0 = 50 CLKB CLKB TS8308500 DR/DRB Z0 = 50 D0/D0B Z0 = 50 Z0 = 50 D7/D7B Z0 = 50 Differential OR/ORB Z0 = 50...

  • Page 7: Board Mechanical Characteristics

    Power planes = V ground plane PLUSD The TSEV8308500 is a seven-layer PCB constituted by four copper layers and three dielectric layers. The four metal layers correspond respectively from top to bottom to the AC and DC sig- nals layer (layer 1), two ground layers (layers 3 and 5), and one supply layer (layer 7).

  • Page 8: Analog Input, Clock Input And De-Embedding Fixture Accesses

    For ADC functions settings accesses (GORB, Die junction temp., ADC gain adjust), smaller 2 mm section banana jacks are provided. Settings Accesses A potentiometer is provided for ADC gain adjust. TSEV8308500 Evaluation Board User Guide 0968D–BDC–01/09 e2v semiconductors SAS 2009...

  • Page 9: Layout Information

    The output data traces lengths are matched to within 0.25 inch (6 mm) to minimize the data output delay skew. For the TSEV8308500 the propagation delay is approximately 6.1 ps/mm (155 ps/inch). The RO4003 typical dielectric constant is 3.4 at 10 GHz.

  • Page 10: Power Supplies

    7 V and V supply planes. Ground pads connections: – The analog ground pads are denoted GND. The corresponding GND pad numbers are 20, 26, 28, 33, 35, 37. TSEV8308500 Evaluation Board User Guide 0968D–BDC–01/09 e2v semiconductors SAS 2009...

  • Page 11: Operating Procedures And Characteristics

    This section describes a typical single-ended configuration for analog inputs and clock inputs. The single-ended configuration is preferable, as it corresponds to the most straightfor- ward and quickest TSEV8308500 board setting for evaluating the TS8308500 at full speed in the military temperature range. The inverted analog input V and clock input CLKB common mode level is Ground (on-board 50Ω...

  • Page 12: Electrical Characteristics

    Long exposure to maximum rating may affect device reliability. The use of a ther- mal heat sink is mandatory. 2. In case only one supply is used for supplying the -5V negative power planes, apply the V absolute maximum ratings. TSEV8308500 Evaluation Board User Guide 0968D–BDC–01/09 e2v semiconductors SAS 2009...
  • Page 13 Clock input impedance – – – Clock inputs voltage compatibility (Single-ended or – ECL levels or 4 dBm (typ.) into 50Ω – differential) (See Application Notes) Clock input power level into 50Ω termination resistor – TSEV8308500 Evaluation Board User Guide 0968D–BDC–01/09...
  • Page 14 Operating Procedures and Characteristics TSEV8308500 Evaluation Board User Guide 0968D–BDC–01/09 e2v semiconductors SAS 2009...

  • Page 15: Application Information

    If ST2 is left floating or tied to V , the data output format is true Binary, If ST2 is tied to GND, the data outputs are in Gray format. TSEV8308500 Evaluation Board User Guide 0968D–BDC–01/09 e2v semiconductors SAS 2009...

  • Page 16: Adc Gain Adjust

    50Ω network analyzer test ports. Impedance mismatch will cause ripple in the S21 parameter as a function of both the degree of mismatch and the length of the line. TSEV8308500 Evaluation Board User Guide 0968D–BDC–01/09 e2v semiconductors SAS 2009...

  • Page 17: Temperature Monitoring And Data Ready Reset Function

    The measurement setup is described in Figure 4-2. The diode VBE forward voltage ver- sus junction temperature (in steady state conditions) is given in Figure 4-3. Figure 4-2. TS8308500 Die Junction Temperature Measurement Setup ∅ 2 mm banana connectors I-GND Pads I-DIODE V-DIODE NP1032C2 V-GND TSEV8308500 Evaluation Board User Guide 0968D–BDC–01/09...

  • Page 18: Data Ready Output Signal Reset

    The Data ready output signal restarts on DRRB command rising edge, ECL logical high levels (-0.8V). DRRB may also be grounded, or is allowed to float, for normal free running Data ready output signal. TSEV8308500 Evaluation Board User Guide 0968D–BDC–01/09 e2v semiconductors SAS 2009...

  • Page 19: Test Bench Description

    Tunable delay line Figure 4-5. Single-ended Analog and Clock Input Configuration Signal Generator Signal Generator (50Ω) CLKB CLK (4 dBm) 8 Data VINB TS8308500 Data Acquisition (50Ω) System -2 dBm GPIB Tunable delay line TSEV8308500 Evaluation Board User Guide 0968D–BDC–01/09...
  • Page 20 Application Information TSEV8308500 Evaluation Board User Guide 0968D–BDC–01/09 e2v semiconductors SAS 2009...

  • Page 21: Package Description

    Section 5 Package Description TS8308500GL Pinout Figure 5-1. TS8308500GL Pinout (CBGA68 Package) VPLUSD DVEE VPLUSD VPLUSD DVEE VPLUSD Gorb GAIN VINB CLKB Diode Ball A1 Index other side BOTTOM VIEW TSEV8308500 Evaluation Board User Guide 0968D–BDC–01/09 e2v semiconductors SAS 2009...
  • Page 22 If the subsequent LVDS circuitry can withstand a lower level for input common mode, it is recommended to lower the positive digital supply level in the same proportion in order to spare power dissipation. TSEV8308500 Evaluation Board User Guide 0968D–BDC–01/09...

  • Page 23: Thermal Characteristics

    Cooling system efficiency can be monitored using the Temperature Sensing Diode, inte- External Heatsink grated in the device. Figure 5-3. CBGA68 Board Assembly 50.5 24.2 20.2 32.5 0.65 Board Note: Dimensions are given in mm. TSEV8308500 Evaluation Board User Guide 0968D–BDC–01/09...
  • Page 24 -40° C < Tc; Tj < 110° C TSEV8308500GL CBGA 68 Ambient Prototype Evaluation Board (delivered with heatsink) TSEV8308500GLZA2 CBGA 68 Ambient Prototype Evaluation Board with digital output buffers (delivered with heatsink) TSEV8308500 Evaluation Board User Guide 0968D–BDC–01/09 e2v semiconductors SAS 2009...

  • Page 25: Schematics

    Section 6 Schematics TSEV8308500 Please, see the following figures. Electrical Schematics TSEV8308500 Evaluation Board User Guide 0968D–BDC–01/09 e2v semiconductors SAS 2009...
  • Page 26 Schematics Figure 6-1. TSEV8308500 Electrical Schematic TSEV8308500 Evaluation Board User Guide 0968D–BDC–01/09 e2v semiconductors SAS 2009...
  • Page 27 VDD = -2V D0 → D7, OR, DR Z0 = 50 To output connector Z0 = 50 OUTb D0B → D7B, ORB, MC100EL VEET = -5V 10 nF 10 nF 100 pF 100 pF TSEV8308500 Evaluation Board User Guide 0968D–BDC–01/09...

  • Page 28: Evaluation Board Schematics

    Schematics Evaluation Board Schematics Figure 6-4. Component Side Description Figure 6-5. Ground Plane Figure 6-6. Power Supplies Planes Figure 6-7. TSEV8308500 Evaluation Board: Component Placement TSEV8308500 Evaluation Board User Guide 0968D–BDC–01/09 e2v semiconductors SAS 2009...
  • Page 29 Whilst e2v has taken care to ensure the accuracy of the information contained herein it accepts no responsibility for the consequences of any use thereof and also reserves the right to change the specification of goods without notice. e2v accepts no liability beyond that set out in its standard conditions of sale in respect of infringement of third party patents arising from the use of tubes or other devices in accordance with information contained herein.

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