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e2v AT84CS001-EB User Manual

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AT84CS001-EB Evaluation Board
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User Guide

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Summary of Contents for e2v AT84CS001-EB

  • Page 1 AT84CS001-EB Evaluation Board ....................User Guide...

  • Page 3: Table Of Contents

    4.4.2 CLKDACTRL ....................2 4.4.3 DACTRL ....................3 4.4.4 RS, DRTYPE, DAEN, BIST, CLKTYPE, SLEEP, STAGG .......4 4.5 Test bench Description ...................6 Section 5 Package Information ................1 5.1 AT84CS001 Pinout ..................1 5.2 Package Outline .....................5 Section 6 AT84CS001-EB Evaluation Board User Guide 0904C–BDC–09/07...
  • Page 4 Ordering Information ................1 Section 7 Appendix ....................1 7.1 AT84CS001-EB Electrical Schematics ............1 7.2 AT84CS001-EB Board Layers ................5 AT84CS001-EB Evaluation Board User Guide 0904C–BDC–09/07...

  • Page 5: Introduction

    Five SMA caps for DAI, DAIN, DAO, DAON and ASYNCRST signals Seven jumpers for the DMUX function settings (RS, BIST, CLKTYPE, DRTYPE, SLEEP, STAGG, DAEN) This user guide uses the AT84CS001-EB evaluation Kit as an evaluation and demon- stration platform and provides guidelines for its correct use. Description The AT84CS001-EB evaluation board is very straightforward as it only implements the AT84CS001 1:2/4 10-bit 2.2 GHz DMUX device, SMA connectors for the standalone...
  • Page 6 The board dimensions are 220 mm x 230 mm. The board comes fully assembled and tested, with the AT84CS001 installed. Figure 1-1. Simplified Schematics of the AT84CS001-EB Evaluation Board DAO/DAON DAI/DAIN 3.3V GND...

  • Page 7: Hardware Description

    Copper layer Power planes = 3.3V, V and V PLUSD Layer 6 Layer thickness = 200 µm FR4 HTG/dielectric layer Layer 7 Copper thickness = 40 µm Copper layer Lower ground plane = reference plane AT84CS001-EB Evaluation Kit User Guide 0904C–BDC–09/07...

  • Page 8: Data And Clock Input Accesses

    The upper row is dedicated to the data and clock signals The lower row is connected to ground Each output port is separated by a connection to ground, as illustrated in Figure 2-2 on page 2-3. AT84CS001-EB Evaluation Kit User Guide 0904C–BDC–09/07...

  • Page 9: Asyncrst

    V for device power consumption testing purposes. Each incoming power supply is bypassed at the banana jack by a 1 µF Tantalum capac- itor in parallel with a 100 nF chip capacitor. AT84CS001-EB Evaluation Kit User Guide 0904C–BDC–09/07...
  • Page 10 Each power supply is decoupled as close as possible to the AT84CS001 device by 10 nF in parallel with 100 pF surface mount chip capacitors. Note: The decoupling capacitors are superimposed with the 100 pF capacitor mounted first. AT84CS001-EB Evaluation Kit User Guide 0904C–BDC–09/07...

  • Page 11: Operating Characteristics

    All instrumentation and connectors are now connected. 5. Switch on the power supplies (recommended power up sequence: simultaneous or in the following order: V = 3.3V, V = 2.5V and 3.3V). PLUSD AT84CS001-EB Evaluation Kit User Guide 0904C–BDC–09/07...

  • Page 12: Electrical Characteristics

    6. Turn on the RF clock generator 7. Perform an asynchronous reset (ASYNCRST push button) on the device. The AT84CS001-EB evaluation board is now ready for operation in BIST mode. Note: The BIST comprises a 10-bit sequence available on all four ports of the device (sets the AT84CS001 in 1:4 mode).
  • Page 13 LVDS Data/Clock Inputs and Outputs Logic Compatibility LVDS Input Common Mode 1.25 Output Common Mode 1.125 1.25 1.375 Differential input IDIFF Differential output ODIFF Output level "High" 1.25 1.425 Output level "Low" 1.075 1.25 AT84CS001-EB Evaluation Kit User Guide 0904C–BDC–09/07...
  • Page 14 Minimum clock pulse width (low) 0.333 Output rise/fall time for data (20% - TR/TF 80%) Output rise/fall time for Data Ready TR/TF (20% - 80%) Data output delay Data Ready output delay |TOD - TDR| AT84CS001-EB Evaluation Kit User Guide 0904C–BDC–09/07...
  • Page 15 - Synchronized 1:4 mode Clock cycles 0 / 0.5 - Staggered 1:2 mode 0 / 0.5 / 1 / 1.5 - Staggered 1:4 mode Note: Please refer to the device datasheet entitled “ AT84CS001”, reference 0809. AT84CS001-EB Evaluation Kit User Guide 0904C–BDC–09/07...
  • Page 16 Operating Characteristics AT84CS001-EB Evaluation Kit User Guide 0904C–BDC–09/07...

  • Page 17: Application Information

    Data or clock in phase signal 5 0Ω line Data or clock inverted phase signal Digital Outputs The digital outputs (data and Data Ready) are LVDS compatible. The 100Ω differential termination is provided on-board. AT84CS001-EB Evaluation Kit User Guide 0904C–BDC–09/07...

  • Page 18: Dmux Functions

    DMUX input. The delay is controlled via the CLKDACTRL potentiometer. This cell allows you to delay the internal DMUX clock by approximately 250 ps via the CLKDACTRL potentiometer (varying from V /3 to (2 × V )/3). AT84CS001-EB Evaluation Kit User Guide 0904C–BDC–09/07...

  • Page 19: Dactrl

    A standalone delay cell is available (input = DAI/DAIN, output = DAO/DAON, control = DACTRL, enable = DAEN). This cell allows you to delay the incoming signal DAI/DAIN by approximately 250 ps via the DACTRL potentiometer (varying from V /3 to (2 × )/3). AT84CS001-EB Evaluation Kit User Guide 0904C–BDC–09/07...

  • Page 20: Rs, Drtype, Daen, Bist, Clktype, Sleep, Stagg

    Port A = 1010101010 Port B = 1010101010 Port C = 0101010101 Port D = 1010101010 Cycle 1: Port A = 0101010101 Port B = 0101010101 Port C = 1010101010 Port D = 0101010101 AT84CS001-EB Evaluation Kit User Guide 0904C–BDC–09/07...
  • Page 21 Application Information Figure 4-5. Jumper Positions of DMUX Functions STAGG STAGG SLEEP SLEEP CLKTYPE CLKTYPE BIST BIST DAEN DAEN DRTYPE DRTYPE Jumper OUT Jumper ON AT84CS001-EB Evaluation Kit User Guide 0904C–BDC–09/07...

  • Page 22: Test Bench Description

    Fs = ADC sampling data clock source --> Fs AT84AS008 Power supplies Acquisition board GW PPT 10-bit 2.2 Gsps ADC AT84CS001 Power supplies DEMUX GW PPT D0 --> D9 8 channel Clock GPIB bus HP16500C analysis logic LabView AT84CS001-EB Evaluation Kit User Guide 0904C–BDC–09/07...

  • Page 23: Package Information

    VCCD VPLUSD VCCD VPLUSD VPLUSD VCCD VCCD VCCD DGND DGND DGND DGND VPLUSD VPLUSD VPLUSD VCCD VPLUSD VCCD VPLUSD VCCD VPLUSD VPLUSD VPLUSD VPLUSD VCCD CLKDACTRL CLKTYPE BIST DRDN DRCN DORN CORN DACTRL DAEN AT84CS001-EB Evaluation Kit User Guide 0904C–BDC–09/07...
  • Page 24 In-phase (+) digital outputs for port B B0 is B0, B1, B2, B3, B4, B5, B6, B7, B8, B9 B5, B4, B3, B2, C2, D2, E2, F2, G2, H2 the LSB, B9 is the MSB AT84CS001-EB Evaluation Kit User Guide 0904C–BDC–09/07...
  • Page 25 Input clock type Selection signal DRTYPE Output clock type Selection signal CLKDACTRL Clock delay cell control signal DACTRL Standalone delay cell control signal DAEN Standalone delay cell enable signal Ratio selection signal SLEEP Sleep Mode Selection signal AT84CS001-EB Evaluation Kit User Guide 0904C–BDC–09/07...
  • Page 26 Package Information Table 5-1. ASTS8CSO01 Pinout Description (Continued) Symbol Pin Number Function STAGG Staggered output mode selection signal BIST Built-In Self Test selection signal Leave floating AT84CS001-EB Evaluation Kit User Guide 0904C–BDC–09/07...

  • Page 27: Package Outline

    Package Information Package Outline Figure 5-2. Package Outline Schematics AT84CS001-EB Evaluation Kit User Guide 0904C–BDC–09/07...
  • Page 28 Package Information AT84CS001-EB Evaluation Kit User Guide 0904C–BDC–09/07...

  • Page 29: Ordering Information

    Industrial "V" grade AT84CS001VTP EBGA 240 Standard -40°C < T < 110°C Industrial "V" grade AT84CS001VTPY EBGA240 RoHS Standard -40°C < T < 110°C AT84CS001TP-EB EBGA 240 Ambient Prototype Evaluation Kit AT84CS001-EB Evaluation Kit User Guide 0904C–BDC–09/07...
  • Page 30 Ordering Information AT84CS001-EB Evaluation Kit User Guide 0904C–BDC–09/07...

  • Page 31: Appendix

    Section 7 Appendix AT84CS001-EB Electrical Schematics Figure 7-1. Data I/O Electrical Schematic AT84CS001-EB Evaluation Kit User Guide 0904C–BDC–09/07...
  • Page 32 Appendix Figure 7-2. Data I/O Electrical Schematic [2] AT84CS001-EB Evaluation Kit User Guide 0904C–BDC–09/07...
  • Page 33 Appendix Figure 7-3. Electrical Schematic of Power Supplies [1] AT84CS001-EB Evaluation Kit User Guide 0904C–BDC–09/07...
  • Page 34 Appendix Figure 7-4. Electrical Schematic of Power Supplies [2] AT84CS001-EB Evaluation Kit User Guide 0904C–BDC–09/07...
  • Page 35 Appendix Figure 7-5. Electrical Schematic of Power Supplies [3] AT84CS001-EB Evaluation Kit User Guide 0904C–BDC–09/07...

  • Page 36: At84Cs001-Eb Board Layers

    Appendix AT84CS001-EB Board Layers Figure 7-6. Top Layer AT84CS001-EB Evaluation Kit User Guide 0904C–BDC–09/07...
  • Page 37 Appendix Figure 7-7. Bottom Layer Figure 7-8. Equipped Board (Top) AT84CS001-EB Evaluation Kit User Guide 0904C–BDC–09/07...
  • Page 38 Appendix Figure 7-9. Equipped Board (Bottom) AT84CS001-EB Evaluation Kit User Guide 0904C–BDC–09/07...
  • Page 39 Whilst e2v has taken care to ensure the accuracy of the information contained herein it accepts no responsibility for the consequences of any use thereof and also reserves the right to change the specification of goods without notice. e2v accepts no liability beyond that set out in its stan- dard conditions of sale in respect of infringement of third party patents arising from the use of tubes or other devices in accordance with informa- tion contained herein.

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