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e2v TSEV8388B User Manual

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ADC 8-bit 1 Gsps TSEV8388B
Evaluation Board
..............................................................................................
User Guide

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Summary of Contents for e2v TSEV8388B

  • Page 1 ADC 8-bit 1 Gsps TSEV8388B Evaluation Board ....................User Guide...

  • Page 3: Table Of Contents

    SMA Connectors and Microstrip Lines De-embedding Fixture ....4-2 Temperature Monitoring and Data Ready Reset Function......4-3 4.7.1 TS8388B ADC Diode Junction Temperature Measurement Setup ..4-3 Data Ready Output Signal Reset ..............4-4 Test Bench Description ................4-5 TSEV8388B - Evaluation Board User Guide 0973D–BDC–02/09 e2v semiconductors SAS 2009...
  • Page 4 Thermal Resistance from Junction to Case: Rthjc ......5-8 5.5.3 Heatsink....................5-8 Ordering Information .................5-9 Section 6 Schematics ................... 6-1 TSEV8388B Electrical Schematics ............6-1 Evaluation Board Schematics ..............6-4 6.2.1 CBGA68 Option..................6-4 6.2.2 CQFP68 Option ..................6-6 TSEV8388B - Evaluation Board User Guide 0973D–BDC–02/09 e2v semiconductors SAS 2009...

  • Page 5: Overview

    Overview Description The TSEV8388B Evaluation Board (EB) is a prototype board which has been designed in order to facilitate the evaluation and the characterization of the TS8388B device up to its 1.8 GHz full power bandwidth at up to 1 Gsps in the extended temperature range.

  • Page 6: Tsev8388B Evaluation Board

    V-GND DRRB CAL1 L = 65 mm typ = LVIN/VINb = LCLK/CLKb CAL2 V-GND CAL3 L = 18 mm typ CAL4 VEET VEEA Short-circuit possibility here VEED MC100EL16 SUPPLIES TSEV8388B - Evaluation Board User Guide 0973D–BDC–02/09 e2v semiconductors SAS 2009...

  • Page 7: Board Mechanical Characteristics

    Power planes = V ground plane PLUSD The TSEV8388B is a seven-layer PCB constituted by four copper layers and three dielectric layers. The four metal layers correspond respectively from top to bottom to the AC and DC sig- nals layer (layer 1), two ground layers (layers 3 and 5), and one supply layer (layer 7).

  • Page 8: Analog Input, Clock Input And De-Embedding Fixture Accesses

    For ADC functions settings accesses (GORB, Die junction temp., ADC gain adjust), smaller 2 mm section banana jacks are provided. Settings Accesses A potentiometer is provided for ADC gain adjust. TSEV8388B - Evaluation Board User Guide 0973D–BDC–02/09 e2v semiconductors SAS 2009...

  • Page 9: Layout Information

    The output data traces lengths are matched to within 0.25 inch (6 mm) to minimize the data output delay skew. For the TSEV8388B the propagation delay is approximately 6.1 ps/mm (155 ps/inch). The RO4003 typical dielectric constant is 3.4 at 10 GHz.

  • Page 10: Power Supplies

    7 V and V supply planes. Ground pads connections: – The analog ground pads are denoted GND. The corresponding GND pad numbers are 20, 26, 28, 33, 35, 37. TSEV8388B - Evaluation Board User Guide 0973D–BDC–02/09 e2v semiconductors SAS 2009...

  • Page 11: Operating Procedures And Characteristics

    This section describes a typical single-ended configuration for analog inputs and clock inputs. The single-ended configuration is preferable, as it corresponds to the most straightfor- ward and quickest TSEV8388B board setting for evaluating the TS8388B at full speed in the military temperature range. The inverted analog input V and clock input CLKB common mode level is Ground (on-board 50Ω...

  • Page 12: Electrical Characteristics

    Long exposure to maximum rating may affect device reliability. The use of a ther- mal heat sink is mandatory. – 2. In case only one supply is used for supplying the 5V negative power planes, apply the V absolute maximum ratings. TSEV8388B - Evaluation Board User Guide 0973D–BDC–02/09 e2v semiconductors SAS 2009...

  • Page 13: Operating Charcteristics

    – – – Clock inputs voltage compatibility (Single-ended or – ECL levels or 4 dBm (typ.) into 50Ω – differential) (See Application Notes) – Clock input power level into 50Ω termination resistor – TSEV8388B - Evaluation Board User Guide 0973D–BDC–02/09...
  • Page 14 Operating Procedures and Characteristics TSEV8388B - Evaluation Board User Guide 0973D–BDC–02/09 e2v semiconductors SAS 2009...

  • Page 15: Application Information

    If ST2 is left floating or tied to V , the data output format is true Binary, If ST2 is tied to GND, the data outputs are in Gray format. TSEV8388B - Evaluation Board User Guide 0973D–BDC–02/09 e2v semiconductors SAS 2009...

  • Page 16: Adc Gain Adjust

    50Ω network analyzer test ports. Impedance mismatch will cause ripple in the S21 parameter as a function of both the degree of mismatch and the length of the line. TSEV8388B - Evaluation Board User Guide 0973D–BDC–02/09 e2v semiconductors SAS 2009...

  • Page 17: Temperature Monitoring And Data Ready Reset Function

    The measurement setup is described in Figure 4-2. The diode VBE forward voltage ver- sus junction temperature (in steady state conditions) is given in Figure 4-3. Figure 4-2. TS8388B Diode Junction Temperature Measurement Setup ∅ 2 mm banana connectors I-GND Pads I-DIODE V-DIODE NP1032C2 V-GND TSEV8388B - Evaluation Board User Guide 0973D–BDC–02/09...

  • Page 18: Data Ready Output Signal Reset

    The Data ready output signal restarts on DRRB command rising edge, ECL logical high levels (-0.8V). DRRB may also be grounded, or is allowed to float, for normal free running Data ready output signal. TSEV8388B - Evaluation Board User Guide 0973D–BDC–02/09 e2v semiconductors SAS 2009...

  • Page 19: Test Bench Description

    GPIB Tunable delay line Note: The TS81102G0 DMUX device can be used at the ADC output in order to slow down the ADC output data rate by a factor of 4 or 8. TSEV8388B - Evaluation Board User Guide 0973D–BDC–02/09...
  • Page 20 Application Information TSEV8388B - Evaluation Board User Guide 0973D–BDC–02/09 e2v semiconductors SAS 2009...

  • Page 21: Package Description

    Package Description TS8388BGL Pinout Figure 5-1. TS8388BGL Pinout of CBGA68 Package VPLUSD DVEE VPLUSD VPLUSD DVEE VPLUSD Gorb GAIN VINB CLKB Diode Ball A1 Index other side BOTTOM VIEW TSEV8388B - Evaluation Board User Guide 0973D–BDC–02/09 e2v semiconductors SAS 2009...
  • Page 22 If the subsequent LVDS circuitry can withstand a lower level for input common mode, it is recommended to lower the positive digital supply level in the same proportion in order to spare power dissipation. TSEV8388B - Evaluation Board User Guide 0973D–BDC–02/09...

  • Page 23: Ts8388Bf/Ts8388Bfs Pinout

    17 16 15 14 13 12 11 10 Pin 1 index VPLUSD VPLUSD GORB TS8388BF/TS8388BFS Gain VINb VINb 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 TSEV8388B - Evaluation Board User Guide 0973D–BDC–02/09...
  • Page 24 If the subsequent LVDS circuitry can withstand a lower level for input common mode, it is recommended to lower the positive digital supply level in the same proportion in order to spare power dissipation. TSEV8388B - Evaluation Board User Guide 0973D–BDC–02/09...

  • Page 25: Cbga68 Thermal Characteristics

    Cooling system efficiency can be monitored using the Temperature Sensing Diode, inte- External Heatsink grated in the device. Figure 5-4. CBGA68 Board Assembly 50.5 24.2 20.2 32.5 0.65 Board Note: Dimensions are given in mm. TSEV8388B - Evaluation Board User Guide 0973D–BDC–02/09...

  • Page 26: Nominal Cqfp68 Thermal Characteristics

    Figure 5-5. Thermal Resistance from Junction to Ambient: Rthja Without heatsink With heatsink Air flow (m/s) 5.4.2 Thermal Resistance Typical value for Rthjc is given to 4.75°C/W. from Junction to Case: Rthjc TSEV8388B - Evaluation Board User Guide 0973D–BDC–02/09 e2v semiconductors SAS 2009...

  • Page 27: Cbga68 Board Assembly With External Heatsink

    Figure 5-6. CQFP68 Board Assembly with a 50 x 50 x 16 mm External Heatsink 28.96 24.13 Printed circuit Aluminum heatsink 15.0 Interface: Af-filled epoxy or thermal conductive grease - 100 μm max. 16.0 50.0 TSEV8388B - Evaluation Board User Guide 0973D–BDC–02/09...

  • Page 28: Enhanced Cqfp68 Thermal Characteristics

    Figure 5-7. Enhanced CQFP68 Suggested Assembly 28.78 24.13 Printed circuit board CuW heatspreader Thermal via Solid ground plane Cooling system efficiency can be monitored using the Temperature Sensing Diode, inte- grated in the device. TSEV8388B - Evaluation Board User Guide 0973D–BDC–02/09 e2v semiconductors SAS 2009...

  • Page 29: Ordering Information

    °C < Tc; Tj < 90°C TS8388BVGL CBGA 68 “V” grade: Standard –40°C < Tc; Tj < 110°C TSEV8388BF CQFP68 Ambient Prototype Evaluation Board Contact e2v for availability TSEV8388BGL CBGA 68 Ambient Prototype Evaluation Board (delivered with heatsink) TSEV8388B - Evaluation Board User Guide 0973D–BDC–02/09...
  • Page 30 Package Description 5-10 TSEV8388B - Evaluation Board User Guide 0973D–BDC–02/09 e2v semiconductors SAS 2009...

  • Page 31: Schematics

    Section 6 Schematics TSEV8388B Please refer to figure 6.1 below. Electrical Schematics TSEV8388B - Evaluation Board User Guide 0973D–BDC–02/09 e2v semiconductors SAS 2009...
  • Page 32 Schematics Figure 6-1. TSEV8388B Electrical Schematic TSEV8388B - Evaluation Board User Guide 0973D–BDC–02/09 e2v semiconductors SAS 2009...
  • Page 33 Figure 6-3. Board Digital Outputs Option Using MC100EL16 Differential Receivers VDD = -2V D0 → D7, OR, DR Z0 = 50 To output connector Z0 = 50 OUTb D0B → D7B, ORB, MC100EL VEET = -5V 10 nF 10 nF 100 pF TSEV8388B - Evaluation Board User Guide 0973D–BDC–02/09...

  • Page 34: Evaluation Board Schematics

    Schematics Evaluation Board Schematics 6.2.1 CBGA68 Option Figure 6-4. Component Side Description Figure 6-5. Ground Plane TSEV8388B - Evaluation Board User Guide 0973D–BDC–02/09 e2v semiconductors SAS 2009...
  • Page 35 Schematics Figure 6-6. Power Supplies Planes Figure 6-7. TSEV8388B Evaluation Board: Component Placement TSEV8388B - Evaluation Board User Guide 0973D–BDC–02/09...

  • Page 36: Cqfp68 Option

    Schematics 6.2.2 CQFP68 Option Figure 6-8. Component Side Description Figure 6-9. Ground Plane TSEV8388B - Evaluation Board User Guide 0973D–BDC–02/09 e2v semiconductors SAS 2009...
  • Page 37 Schematics Figure 6-10. Power Supplies Planes Figure 6-11. TSEV8388B Evaluation Board: Component Placement TSEV8388B - Evaluation Board User Guide 0973D–BDC–02/09...
  • Page 38 Schematics TSEV8388B - Evaluation Board User Guide 0973D–BDC–02/09 e2v semiconductors SAS 2009...
  • Page 39 Whilst e2v has taken care to ensure the accuracy of the information contained herein it accepts no responsibility for the consequences of any use thereof and also reserves the right to change the specification of goods without notice. e2v accepts no liability beyond that set out in its standard conditions of sale in respect of infringement of third party patents arising from the use of tubes or other devices in accordance with information contained herein.

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