Analog Devices EVAL-SSM3525Z User Manual page 7

EVAL-SSM3525Z User Guide
BCLK_3525
FSYNC_3525
SDATAI_3525
SDATAO_3525
C43
10pF
SCL_3525
SDA_3525
IOVDD
2
J25
R44
47kΩ
+5V
AVDD_3525
J23
1
2
2-Jumper
10µF
IOVDD
2 1
J17
10µF
R31
C44 C45 C46
49.9Ω
10pF 10pF 10pF
1
ADDR
Figure 7. Schematic of the EVAL-SSM3525Z Evaluation Board
C29 C26
0.10µF
C19
C17
0.10µF
BCLK_3525
E5
BCLK
FSYNC_3525 D5
FSYNC
SDATAI_3525
E3
SDATAI
E4
SDATAO
SCL_3525
E1
SCL
SSM3525
SDA_3525
E2
SDA
ADDR
D3
ADDR
Rev. 0 | Page 7 of 16
PVDD
TP14
C15 C13
0.10µF 10µF
TP3
A5
BST+
A4
OUT+
B4
OUT+
U8
A2
OUT–
B2
OUT–
TP9
A1
BST–
SSM3525 Section
UG-1183
C39 C40
10nF 10nF
OUT+
OUT–