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Embedded Artists AB. Disclaimer Embedded Artists AB makes no representation or warranties with respect to the contents hereof and specifically disclaim any implied warranties or merchantability or fitness for any particular purpose. Information in this publication is subject to change without notice and does not represent a commitment on the part of Embedded Artists AB.
Page 4: External Memories 3.1.4 Page 5: Expansion Connector Usage of CPU Pins LPC3131/41 OEM Board Mechanical Dimensions and Connector Things to note about the LPC3131/41 OEM Board 3.4.1 NAND FLASH Bad Block 3.4.2 Brand of Memory Chips 4 LPC31xx Base Board Design...
LPC3131/41 Developer’s Kit - User’s Guide Page 5 1 Document Revision History Revision Date Description 2009-03-09 First complete version. Add description about booting and correct language and spelling errors. 2009-04-11 Update description of MMC/SD card detect fix and codec handling.
LPC3131/41 microcontroller. This document is a User’s Guide that describes the LPC3131/41 OEM Board and the LPC31xx Base Board hardware design. It is the User’s Manual for both the LPC3131/41Developer’s Kit as well as for just the LPC3131/41 OEM Board.
ESD. Never touch directly on the LPC3131/41 OEM Board and in general as little as possible on the LPC31xx Base Board. The keys on the LPC31xx Base Board have grounded shields to minimize the effect of ESD.
LPC3131/41 Developers Kit. Due to the nature of the LPC3131/41 Developers Kit – an evaluation board not for integration into an end-product – fast transient immunity tests and conducted radio-frequency immunity tests have not been executed.
I2C channel is disconnected via R56/R57 (which are 0 ohm resistors/jumpers that are not mounted). R56/R57 is the only thing that differs between v1.0 and v1.1 of the board. On v1.0, the I2C1 of the LPC3131/41 is always connected to the LTC3447.
3.1.2 Page 3: LPC3131/41 CPU Page 3 of the schematic contains the core part of the design, which of course is the LPC3131/41 microcontroller. It is an ARM926EJ-S cpu core with a lot of different peripheral units and on-chip memory (192 KByte SRAM).
NAND band 0-3 (accessible via NAND flash controller, not directly via memory address) The LPC3131/41 OEM Board uses the external SDRAM bank 0 as well as NAND bank 0. It is mainly the two external SRAM banks that are available for the off-board external memory interface of the LPC3131/41 OEM Board.
The data bus buffer is controlled by the signal N_DBUF_EN. By pulling this signal low, the data bus buffer is enabled. The buffered version of the LPC3131/41 signal OE controls the direction of the data bus buffer. During read operations the buffer acts as an input and during write operations it acts as an output.
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LPC3131/41 Developer’s Kit - User’s Guide Page 14 SYSCLK_O EBI_D0-EBI_D15 Yes, but only available via the data bus buffer MLCD_A0/ALE Yes, but only available via the address bus buffer MLCD_A1/CLK MLCD_DB2/EBI_A2 MLCD_DB3/EBI_A3 MLCD_DB4/EBI_A4 MLCD_DB5/EBI_A5 MLCD_DB6/EBI_A6 MLCD_DB7/EBI_A7 MLCD_DB8/EBI_A8 MLCD_DB9/EBI_A9 MLCD_DB10/EBI_A10 MLCD_DB11/EBI_A11...
NAND flash and SDRAM. The lifetime of memory chips is limited and availability can also be limited from time to time. Embedded Artists make every effort to mount the original design chip on the board. In case that is impossible a compatible chip will instead be mounted without any prior notice. There can be small programming differences between mounted brands.
LPC3131/41 OEM Board. Usage of CPU Pins Almost all pins of the LPC3131/41 are directly available on the expansion connectors. Only in a few cases are pins used for dedicated functionality like (dynamic) memory control signals and chip select signals.
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LPC3131/41 Developer’s Kit - User’s Guide Page 17 I2STX_WS0 I2STX_DATA0 Can be used to control powering of MMC/SD memory card interface. I2STX_BCK0 Can be used to detect MMC/SD memory card presence. I2SRX_DATA1 Can be connected to UDA1380 codec. I2SRX_WS1 I2SRX_BCK1...
The codec, uda1380 (U12), communicate audio data over the I2S bus and command/setting data over the I2C1 bus. Transferring I2S data reliable from the codec to the LPC3131/41 requires booting from JTAG or USB. UART and SPI booting can create an unreliable connection. The problem is under investigation.
LPC3131/41 Developer’s Kit - User’s Guide Page 19 4.2.3 SD/MMC card detect The pull-up on SD card detect pin is after the power switch. Due to this there is a need to enable power to the SD/MMC slot to even detect the card insertion.
The LPC31xx Base Board has a number of jumpers in order to be able to connect/disconnect and fully utilize all functionality of the LPC3131/41 and the LPC31xx Base Board. Figure 2 below illustrates all jumpers and explains to what part of the design they belong. Note that v2.0 of the board is shown.
LPC3131/41 Developer’s Kit - User’s Guide Page 21 4.3.1 Default Jumper Positions Figure 3 below illustrates the default jumper positions as mounted when the board is delivered from Embedded Artists. Figure 3 – LPC31xx Base Board Default Jumper Positions 4.3.2 Illegal Jumper Combinations Note that some jumpers are mutual exclusive and should not be inserted simultaneously.
LPC3131/41 Developer’s Kit - User’s Guide Page 22 Connectors Figure 4 below illustrate the position of all external connectors on the LPC31xx Base Board. Mic in Line in 1 Headphone MMC/SD RS232 DSUB Power in Line in 2/ XBee Line out...
LPC3131/41 Developer’s Kit - User’s Guide Page 23 Important Components Figure 5 below illustrates the position on the LPC31xx Base Board for some important components in the design. Voltage measurement SD/MMC pads and Trimming Power potentiometer Power LED Accelerometer for analog...
Board is formed by AND:ing N_STCS0 and N_STCS1. This, in turn, enables the databus buffer (U16 on LPC3131/41 OEM Board) when the DBUF_EN jumper (pin 1-2 on J40) is inserted on the LPC31xx Base Board. See Figure 7 to locate DBUF_EN jumper on the LPC31xx Base Board.
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For the XNOR gate the output is high when both inputs are low. This will also solve the problem, since the databus buffer (U16 on LPC3131/41 OEM Board) will not be enabled during NAND boot when both N_STCS0 and N_STCS1 are low.
The LPC31xx Base Board contains a USB-to-Serial bridge chip (FT232R from FTDI) that connects the UART channel on the LPC3131/41 to a virtual COM port on the PC (via USB). It is this serial channel that is the console interface to the system.
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LPC3131/41 Developer’s Kit - User’s Guide Page 28 The new COM port (USB Serial Port) will be listed under the Ports list. Right-click on the new USB Serial Port and select Properties, as illustrated in Figure 10 below. USB Serial Port Properties Figure 10 –...
0x1102 9000. The boot code can handle boot images up to 128 kByte in size on the LPC3131/41. For larger applications, the booting has to be done in more steps, i.e., a second stage boot loader has to be added.
The LPC3131/41 User’s Manual from NXP contains all details about booting including the pre-defined MMU table. The rest of this section gives an overview of what is supported by the LPC3131/41 OEM Board and LPC31xx Base Board, and how to quickly get started with the download process.
-I elf32-little -O binary --strip-debug --strip-unneeded --verbose <input-file> lpc313x.bin The second step is to create a CRC attached boot image for the LPC3131/41. There is a command line tool from NXP, bundled in the CDL package named: lpc313xImgCreator. See program output explaining the command line options below.
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LPC3131/41 Developer’s Kit - User’s Guide Page 32 The -o option specifies the output directory (the current directory in this case). The -pc option specifies that a CRC header should be appended. The -i option specifies the input file. An output file called lpc313x.rom will be generated in the command line example above.
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LPC3131/41 Developer’s Kit - User’s Guide Page 34 5.3.2.3 uVision from Keil Under uVision (Keil’s IDE), the command to create a binary file, named lpc313x.bin is as shown below. The input file is in this case typically the output file with axf-ending.
5.3.4 Booting via SPI NOR flash When booting via SPI the boot image is downloaded from the SPI NOR flash into LPC3131/41 internal RAM immediately after reset. Execution is also started immediately after download. No message is sent to the UART channel.
When booting via USB, a special (PC) program must be used to connect to the DFU device that the boot code implements in the LPC3131/41. Follow the list below to download a boot image. 1. Connect a USB cable (mini-B to A) from your computer to the LPC31xx Base Board. Note that it is the LPC3131/41 USB connection that should be connected to, not the UART-to-serial bridge on the LPC31xx Base Board.
Figure 19 – Device Firmware Upgrade Application Screenshot connector (J17) for USB Boot Figure 20 – LPC31xx Base Board USB Connector to LPC3131/41 5.3.6 LED on GPIO2 The boot code will signal any error during boot process by toggling GPIO2 pin. There is a LED connected to this pin for direct visual feedback.
LPC3131/41 Developer’s Kit - User’s Guide Page 38 5.3.7 Booting via NAND Flash NXP has written detailed instructions of how to use the u-boot or Apex bootloaders to program the NAND flash on the LPC31xx OEM Boards with a bootable image. Please follow the links below for more information.
LPC3131/41 Developer’s Kit - User’s Guide Page 39 6 Further Information The LPC3131/41 microcontroller is a complex circuit and there are a number of other documents with more information. The following documents are recommended as a complement to this document. NXP LPC3131 Datasheet http://ics.nxp.com/products/lpc3000/datasheet/lpc3130.lpc3131.pdf...
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