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IC406 ADC0838CCWM
17
D1
18
CS
R
R
5 BIT SHIFT REGISTER
START
SGL/DIF ODD/SIGN SELECT1 SELECT0
16
CLK
VCC
1
CH0*
2
CH1*
3
CH2*
4
CH3*
5
CH4*
6
CH5*
7
CH6*
8
CH7*
9
COM*
12
V
REF
20
V
CC
7V ZENER
19
+
V *
7V ZENER
10
D GND*
INPUT PROTECTION - ALL LOGIC INPUTS
11
A GND
*Some of these functions/plns are not avallable with other options.
IC408 ICS301M-62(XD200U)
VDD GND
2
OTP
ROM
with PLL
Divider
Values
Crystal
1
X1/CLK
or clock
input
Crystal
Oscillator
8
X2
R
R
R
D
C
MUX
ADDRESS
∑
ANALOG
MUX
(EQUIVALENT)
C
TO INTERNAL
CIRCUITRY
R
Vcc
TO
INPUT
INTERNAL
13
CIRCUITS
16
17
18
ICS301M-66(SD200U)
3
PLL
Clock
Synthesis
and Control
Circuitry
Logic and
PDTS (both outputs and PLL)
CS
T D
COMP
COMP
C
R
SAR
LOGIC
AND
LATCH
LADDER
AND
DECODER
COMP
ONE
SHOT
PARALLEL
XFR TO
SHIFT REG
Output
5
CLK
Buffer
Divide
4
REF
Output
Buffer
7
B-5
START CONV AND ENABLE
TSL OUTPUT BUFFER
TIME
DELAY
START
C
L
Q
L2
CS
R
CS
EOC
B7
R
C
B6
B5
8-BIT
B4
C
SHIFT
B3
REGISTER
CS
R
F1
B2
L
B1
B0
EOC
LSB FIRST
MSB FIRST
IC409 NC7SZ02P5X
1
5
V
A
CC
2
B
3
4
GND
Y
FUNCTION TABLE
Y=A+B
Inputs
Outputs
B
Y
A
L
L
H
L
H
L
H
L
L
H
H
L
H = HIGH Logic Level
L = LOW Logic Level
13
SE*
15
SARS*
CS
L Q
L1
C
R
14
Q
DO
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