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abaco systems SBC347A-11330001 Hardware Reference Manual

Sbc347a series vpx single board computer
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Hardware Reference Manual
SBC347A* 3U VPX Single Board Computer
THE SBC347A IS DESIGNED TO MEET THE EUROPEAN UNION (EU) RESTRICTIONS OF
HAZARDOUS SUBSTANCE (RoHS) DIRECTIVE (2002/95/EC) CURRENT REVISION.
Publication No. 500-9300527837-000 Rev. A.0

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Summary of Contents for abaco systems SBC347A-11330001

  • Page 1 Hardware Reference Manual SBC347A* 3U VPX Single Board Computer THE SBC347A IS DESIGNED TO MEET THE EUROPEAN UNION (EU) RESTRICTIONS OF HAZARDOUS SUBSTANCE (RoHS) DIRECTIVE (2002/95/EC) CURRENT REVISION. Publication No. 500-9300527837-000 Rev. A.0...

  • Page 2: Document History

    WEEE is processed in accordance with the requirements of the WEEE Directive. Abaco Systems will evaluate requests to take back products purchased by our customers before August 13, 2005 on a case-by-case basis. A WEEE management fee may apply.

  • Page 3: About This Manual

    About This Manual Conventions Notices This manual may use the following types of notice: WARNING Warnings alert you to the risk of severe personal injury. CAUTION Cautions alert you to system danger or loss of data. NOTE Notes call attention to important features or instructions. Tips give guidance on procedures that may be tackled in a number of ways.

  • Page 4: Further Information

    Further Information Abaco Website You can find information regarding Abaco products on the following website: LINK https://www.abaco.com Abaco Documents This document is distributed via the Abaco website. You may register for access to manuals via the website, whose link is given above. LINKS https://www.abaco.com/products/sbc347a-3u-openvpx-single-board-computer The following is a list of reference documentation related to SBC347A:...
  • Page 5 Technical Support Contact Information You can find technical assistance contact details on the website Embedded Support page. LINK https://www.abaco.com/embedded-support Abaco will log your query in the Technical Support database and allocate it a unique Case number for use in any future correspondence. Alternatively, you may also contact Abaco’s Technical Support via: LINK support@abaco.com...

  • Page 6: Table Of Contents

    Table of Contents 1 • Introduction ..............14 1.1 Features.
  • Page 7 5.3.2 Module Maskable Reset ............... . 38 5.4 I/O.
  • Page 8 6 • FPGA Registers ............. .60 6.1 Board ID Register (0x600).
  • Page 9 6.43 COM Port Modem Configuration Register (0x6A3)..........73 6.44 SATA Port Availability Register (0x6A4).
  • Page 10 A.5.1 Convection-cooled Boards ..............99 A.5.2 Conduction-cooled Boards .
  • Page 11 List of Figures Figure 1-1 ESD Label (Present on Board Packaging) ..........17 Figure 2-1 Product Label (Packaging) .
  • Page 12 List of Tables Table 3-1 P3 Link Setting ............... . . 20 Table 3-2 P4 Link Setting .
  • Page 13 Table A-11 Conduction-cooled Environmental Specifications ......... . 99 Table A-12 Product Options .

  • Page 14: Introduction

    1 • Introduction The Abaco Systems SBC347A* is a member of the VPXcel3 family of 3U VPX ® Intel processor-based single board computers (SBCs). This family is aimed at processing, communications, and display applications in the military and aerospace market.

  • Page 15: Features

    1.1 Features • Intel Broadwell Core i7 Mobile (+ECC) platform-based SBC • Intel fifth generation Core i7 processor, with up to four cores, at up to 2.7 GHz • Up to 16 GBytes of dual channel DDR3 SDRAM with ECC (8 GBytes per controller) •...

  • Page 16: Safety Notices

    1.2 Safety Notices The following general safety precautions represent warnings of certain dangers of which Abaco Systems is aware. Failure to comply with these or with specific Warnings and/or Cautions elsewhere in this manual violates safety standards of design, manufacture and intended use of the equipment. Abaco Systems assumes no liability for the user’s failure to comply with these requirements.

  • Page 17: Handling

    1.2.4 Handling CAUTION Only handle the SBC347A by the edges or front panel. Figure 1-1 ESD Label (Present on Board Packaging) 1.2.5 Heatsink CAUTIONS Do not remove the heatsink. There are no user-alterable components underneath the heatsink, so users should have no reason to remove it. Users should not attempt reattachment of the heatsink, as this requires precise torque on the screws attaching the heatsink to the PCB.

  • Page 18: Unpacking

    Figure 2-1 Product Label (Packaging) SBC347A-11330001 2.2 Inspection When handling the SBC347A, observe antistatic precautions. Visually examine the SBC347A for any physical damage. If the SBC347A is not received in perfect physical condition, report this to Abaco’s Technical Support...

  • Page 19: Configuration

    3 • Configuration 3.1 Link Configuration The SBC347A has push-on jumpers included in the standard kit of parts; additional jumpers may be obtained on request. These are suitable for level 1 to 3 low vibration applications. Figure 3-1 Link Positions The diagram above shows standard 2.54 mm pitch headers for general use.

  • Page 20: Inspection

    3.2 Inspection The SBC347A is shipped from the factory with no jumpers fitted. 3.3 Link Descriptions NOTES Ordinary operation requires no jumpers to be fitted. Software can read the state of the links from the FPGA. Additional jumper link functions are provided by an onboard EEPROM DIP switch device. Section 5.14.2 EEPROM DIP Switch page If you are about to install your board and power up for the first time, leaving your board in the...

  • Page 21: Installation And Power Up/Reset

    4 • Installation and Power Up/Reset Review Section 1.2 ʺSafety Noticesʺon page 16 before installing the SBC347A. The following notices also apply: CAUTION Consult the enclosure documentation to ensure that the SBC347A’s power requirements are compatible with those supplied by the backplane. 4.1 Power Supply Requirements The SBC347A requires the backplane to provide 5 V (VS3) and 3.3 V (VS2 and 3V3_AUX) supplies.

  • Page 22: Board Installation Notes

    4.3 Board Installation Notes 1. The VPX specification allows for a variety of different backplane pinouts depending on the mix of differential and single ended connectors. Ensure that the pinout of the SBC347A matches that of the backplane slot before insertion.

  • Page 23: Connecting To Sbc347A

    4.4 Connecting to SBC347A To interact with onboard firmware requires the SBC347A to have connected, as a minimum, a video display (video graphics array, (VGA)) and a USB keyboard. Ethernet and terminal (COM1) connections may also be required, depending on Operating System requirements.

  • Page 24: Reset And Power-Up Sequence

    4.5 Reset and Power-up Sequence A power sequencer monitors the backplane supply voltages and will shut down the onboard power supplies if the backplane supplies are not within specified limits. Once the backplane supplies are within specification, the SBC347A transitions through its sleep states (S5 to S0) before finally powering up all onboard supplies and executing BIOS Power On Self Test (POST).

  • Page 25: First Boot Menu

    4.7 First Boot Menu This enables the user, for one time only, to select a drive device from which to boot. This feature is useful when installing from a bootable disk. For example, when installing an operating system from a CD, enter this menu and use the arrows keys to highlight ATAPI CD-ROM Drive.

  • Page 26: About The Setup Menus

    4.8 About the Setup Menus The Setup menus are accessed by pressing the key at the very beginning of Delete the boot cycle. The Setup menus have two main areas. The left frame displays status data and the options or sub-menus that can be configured. Here, text in black is for information only, and options and sub-menus are in blue text (or greyed out if unavailable) with sub-menus being distinguished by “”.

  • Page 27: Main Menu

    4.9 Main Menu This is the menu shown on entry to Setup. It reports details on the BIOS firmware, the board and the processor. It also allows the user to set the System Language (English is the default and currently the only option) and the SBC347A clock/ calendar (although without battery backup, any power cycle will reset the clock).

  • Page 28: Advanced Menu

    4.10 Advanced Menu This allows configuration of many CPU and chipset settings. CAUTION Changes made from some menus can cause the SBC347A to malfunction. If problems are detected after changes have been made, reboot the board and access the Setup. Select the Save & Exit menu, pick Restore Defaults then save these changes and reboot the board (e.g., by picking Save Changes and Reset).

  • Page 29: Chipset Menu

    4.11 Chipset Menu This allows selection of the various options for the chipsets on the board (for example, the CPU configuration and configurations for the PCH). The settings for the chipsets are processor-dependent; take care when changing settings from the defaults set at the factory.

  • Page 30: Security Menu

    4.12 Security Menu This menu allows setup of both an Administrator and a User password. The on- screen description covers use of these passwords. If both passwords are to be used, the Administrator password must be set first. Figure 4-5 Security Menu CAUTION Take care when setting passwords.

  • Page 31: Boot Menu

    4.13 Boot Menu This sets the priority of the boot devices, including booting from a remote network. The devices shown in this menu are the bootable devices detected during POST. If an installed drive does not appear, verify the hardware installation.

  • Page 32: Save & Exit Menu

    4.14 Save & Exit Menu This provides options on saving Setup selections and exiting Setup. Figure 4-7 Save & Exit Menu If changes have previously been made from the Setup menus, and the SBC347A malfunctions, reboot the board and select this screen. Pick Restore Defaults then save these changes and reboot the board (e.g., by picking Save Changes and Reset).

  • Page 33: Event Logs Menu

    4.15 Event Logs Menu This menu provides option of changing settings of event logs or viewing event logs. Figure 4-8 Event Logs Menu Publication No. 500-9300527837-000 Rev. A.0 Installation and Power Up/Reset 33...

  • Page 34: Functional Description

    5 • Functional Description Figure 5-1 Block Diagram NOTES Due to the increasingly short lifetimes of system components, the I/O devices used on the SBC347A are not guaranteed to remain fixed in the future. Hardware should be accessed only through mechanisms provided by the Operating System's Board Support Package, and not directly by application software.

  • Page 35: Microprocessor Subsystem

    5.1 Microprocessor Subsystem The core chipset is based on Intel’s Broadwell Core i7 Mobile (+ECC) platform and consists of: • Intel fifth generation Core i7 processor, with up to four cores, at up to 2.7 GHz • Intel 8 Series PCH LINK For more details on the processor and chipset, see http://www.intel.com.

  • Page 36: Series Chipset (Pch)

    5.1.2 8 Series Chipset (PCH) The following features of the PCH are implemented on the SBC347A: • Optional PCIe Gen2 x4 port • Optional PCIe Gen2 x2 port • SATA host controller supporting three ports at 6 Gbits/second (Gen3) (two routed off card) •...

  • Page 37: Flash Hard Drive

    5.2.3 Flash Hard Drive One SATA port from the PCH (port 5) is connected to a Silicon Motion SM631 series SATA SSD. This device integrates a Single Level Cell (SLC) NAND array and a controller with a SATA Gen2 interface. The controller uses ECC and wear- leveling to provide a robust storage area.

  • Page 38: Vpx Interface

    5.3 VPX Interface The interface to the VPX backplane is compatible with the following specifications: • VITA 46.0 • VITA 65 5.3.1 OpenVPX Compatibility The SBC347A is compatible with the following module profiles, as defined by the VITA 65 OpenVPX Specification: •...

  • Page 39: Data Plane Fabric

    5.5 Data Plane Fabric In accordance with the OpenVPX Specification, the top half of the P1 connector allocated for the data plane connection and complies with OpenVPX module profile MOD3-PAY-2F2T-16.2.5-3 (1000BASE-T control plane is capable of 10GBASE-T operation) The OpenVPX fabric connection is made up from an optional x2 PCIe link from the PCH, and the bottom four lanes of the Broadwell CPU PEG port on the VPX P1 connector.

  • Page 40: Control Plane Fabric/Gigabit Ethernet

    5.6 Control Plane Fabric/Gigabit Ethernet The SBC347A supports a total of two 10GBASE-T Ethernet channels, which collectively make up the Control Plane interface. The channels are called ETH0 and ETH1. The actual configuration of the Control Plane depends on the build variant of the SBC347A (described below).

  • Page 41: Usb

    5.7 USB The PCH provides up to four USB2.0 ports using EHCI and XHCI controllers. These ports are called USB0, USB1, USB2, and USB3. Two power switches are used to switch VBUS power to the ports. USB0 and USB1 have separate power pins but share a single power switch (maximum 1 A for each port/pin and 1.5 A for combined load).

  • Page 42: Rs422/Rs485 Mode

    The following table shows the COM1 and COM2 routing to the VPX backplane connectors: Table 5-6 COM1/COM2 Signal Availability Port RS232 Signal RS422/RS485 Signal Pin COM1_RXD COM1_RXDA P1/G11 COM1_TXD COM1_TXDA P1/G9 COM1 COM1_RTS~ COM1_RXDB P2/G3 COM1_CTS~ COM1_TXDB P2/G5 COM2_RXD COM2_RXDA P1/G15 COM2_TXD COM2_TXDA...

  • Page 43: Sata

    5.9 SATA The SBC347A provides up to four SATA interfaces. One port is connected directly to the onboard SSD device, and the other three are routed to the VPX backplane connectors for connection to off-board peripherals such as hard disk drives or CD/DVD drives, as follows: Table 5-7 SATA Signal Availability Port RXP...

  • Page 44: Gpio

    5.10 GPIO The SBC347A provides up to eight lines of GPIO, each with interrupt generation capabilities. Availability of the GPIO signals depends on the build variant. The table below summarizes the availability and signal routing: Table 5-8 GPIO Line Signal Availability GPIO Line P1/A3 P1/B3...

  • Page 45: Video

    5.11 Video 5.11.1 VGA The SBC347A provides a VGA video port to the VPX backplane connector. This port is available on all build options, as follows: Table 5-9 VGA Signal Availability Signal P2 Pin VGA_RED VGA_GREEN VGA_BLUE VGA_HSYNC VGA_VSYNC VGA_DDC_DATA G7 VGA_DDC_CLK The Graphics Controller (GT2) is integrated into the Core i7 processor, and it includes 3D compute elements and multi-format hardware-assisted decoding/...

  • Page 46: Lpc Bus

    5.12 LPC Bus The PCH is the master of an LPC bus, which is connected to the devices below. 5.12.1 FPGA ® ® A Microsemi SmartFusion 2 provides various functions. See Section 5.21 ʺFPGAʺ page 58 for more details. 5.12.2 Trusted Platform Monitor The SBC347A includes a Trusted Platform Monitor (TPM) device as a means to generate and store security key generation.

  • Page 47: I 2 C Bus

    5.14 I C Bus The PCH has a single I C bus, supporting SMBus 2.0. C devices on the board are connected to this bus as shown below: Figure 5-4 I C Bus Structure Elapsed Time (Master) EEPROM Switch Indicator The table below summarizes the I C slave addresses of the devices in the system.

  • Page 48: Eeprom Dip Switch

    5.14.2 EEPROM DIP Switch A PCA9560 device is used to configure the following aspects of board operation: Table 5-12 DIP Switch Options Output Function (Datasheet Name) MUX_A Reserved MUX_B Configuration EEPROM write enable 0 = Writes to configuration EEPROM devices are only enabled when NVMRO MUX_C is inactive and when the configuration EEPROM jumper link is fitted (default) 1 = Writes to configuration EEPROM enabled whenever NVMRO is inactive...

  • Page 49: Board Management Microcontroller (Optional)

    5.15 Board Management Microcontroller (optional) The SBC347A contains an optional microcontroller functioning as a BMM for implementation of the VPX System Management function in accordance with VITA 46.11. The BMM is connected to the following interfaces: • RS232 interface (connected to COM3) •...

  • Page 50: Power Manager/Monitor

    5.15.1 Power Manager/Monitor The SBC347A uses a Lattice ispPOWR-1014A programmable power manager to control all of the onboard power supplies to meet supply sequencing requirements. See Section 5.17 ʺPower Sequencingʺ page 52 for more information. LINK For more details on the Power Manager device, see http://www.latticesemi.com. In addition to controlling the onboard supplies, the power manager also monitors each rail, and its voltage can be read from registers internal to the device, across the I...

  • Page 51: Timers

    5.16 Timers 5.16.1 General Purpose Timers The timer/counter block within the PCH contains three counters that are equivalent in function to those found in one 82C54 programmable interval timer. These three counters are combined to provide the system timer function and speaker tone.

  • Page 52: Power Sequencing

    5.17 Power Sequencing 5.17.1 Onboard Sequencing The Lattice ispPOWR Power Manager device sequences the power supplies in the required order for onboard devices per Section 5.15.1 ʺPower Manager/ Monitorʺ page 50. It also monitors the backplane supply voltages and shuts down the onboard supplies if these fall below their specified levels.

  • Page 53: Leds

    5.18 LEDs Figure 5-6 Rear LED Positions '6 '6 '6 '6 '6 '6 '6 '6 Table 5-15 LED Meanings LEDs Name Color Meaning When Lit DS401 BIT Fail Indicates that BIT has failed, or another OS is not able to switch it off DS402 BIT Status 1 Yellow...

  • Page 54: Bit Leds (Ds401 To Ds404)

    5.18.1 BIT LEDs (DS401 to DS404) The SBC347A has four software-controlled LEDs, to reflect the status of BIT or other boot software. When used by BIT, the LEDs have the following meanings: Table 5-16 BIT LED Meanings LEDs Color Meaning When Lit DS401 BIT Fail DS404...

  • Page 55: Sleep Status Led (Ds406)

    5.18.3 Sleep Status LED (DS406) This yellow LED illuminates when the SBC347A is in one of the S3, S4, or S5 sleep states. It is used with DS407 (see below) to indicate the power state, as follows: Table 5-18 Power States DS406 DS407 Power State...

  • Page 56: Jtag

    5.19 JTAG 5.19.1 Boundary Scan The SBC347A provides JTAG boundary scan facilities for all IEEE 1149.1 and IEEE 1149.6-compliant devices. Access to the main chain is via the VPX backplane Connector, and access to the CPU and PCH chain is via the test access card (TAC).

  • Page 57: Resets And Interrupts

    5.20 Resets and Interrupts 5.20.1 Interrupt Controllers The PCH provides an industry standard architecture (ISA) compatible Programmable Interrupt Controller (PIC) that incorporates the functionality of two 82C59 interrupt controllers. These are cascaded so that 14 external and two internal interrupts are possible. In addition, the PCH supports a serial interrupt scheme.

  • Page 58: Fpga

    5.21 FPGA The FPGA is a Microsemi SmartFusion2 device that provides the following facilities: • Board Configuration, Control and Status registers • Three UARTs (COM1 to COM3) • Watchdog timer • GPIO controller • General purpose timers • NVRAM interface •...

  • Page 59: Front Panel

    5.22 Front Panel 5.22.1 Air-cooled Versions (Build Levels 1 to 3) Figure 5-8 Air-cooled Front Panel VITA 48 1” Pitch 5.22.2 Conduction-cooled Versions (Build Levels 4 and 5) Figure 5-9 Conduction-cooled Front Panel Publication No. 500-9300527837-000 Rev. A.0 Functional Description 59...

  • Page 60: Fpga Registers

    6 • FPGA Registers The FPGA provides the registers shown below for controlling or reading the status of the hardware. They appear in LPC I/O space at addresses 0x600 to 0x6FF. Table 6-1 FPGA Registers LPC I/O Port Description Access LPC I/O Port Description Access...

  • Page 61: Board Id Register (0X600)

    LPC I/O Port Description Access LPC I/O Port Description Access 0x6AA VGA Display Availability Read only 0x6BE COM Port Loopback Enable Read/Write 0x6AB DVI/HDMI Display Availability Read only 0x6BF SSD Erase Control Read/Write 0x6AC Display-Port Display Availability Read only 0x6C0 SSD Cache Flush Control Read/Write 0x6AD...

  • Page 62: Watchdog Timer Refresh Register (0X60D)

    6.4 Watchdog Timer Refresh Register (0x60D) Any write access to this register reloads the Watchdog Timer (WDT). This must be done periodically after the WDT is enabled to keep the WDT from causing a board reset. Any read access returns 0x00. 6.5 Watchdog Timer Control and Status Register LS Byte (0x60E) Bits Read/Write...

  • Page 63: Bmm/Bmc Control Register (0X620)

    6.8 BMM/BMC Control Register (0x620) Bits Read/Write Description Default 7 to 5 Read only Reserved Read only Reserved Read only Reserved Read only Reserved Read only Reserved Read only Reserved 6.9 LED Control Register (0x622) Bits Read/Write Description Default Read/Write BIT Pass LED (DS404): 0 (sticky on BIT reset) 1 = LED lit...

  • Page 64: Bit Control And Status Register (0X629)

    6.11 BIT Control and Status Register (0x629) Bits Read/Write Description Default Read/Write HRESET request: 1 = Board reset requested 0 = Board reset not requested 6 and 5 Read/Write BIT run status: 00b (sticky when reset using HRESET request) 00 = BIT not previously run 01 = Fast BIT performed 10 = Full BIT performed 11 = Fast Start performed...

  • Page 65: Axis Clock Frequency Register (0X64E)

    6.14 AXIS Clock Frequency Register (0x64E) This returns the AXIS master clock period in nanoseconds. It returns the value 0xB4, which equals 180 ns, giving a 5.556 MHz clock. 6.15 AXIS Clock Control Register (0x64F) Bits Read/Write Description Default Read/Write AXIS master enable: 1 = Drive AXIS clock onto GPIO2 and allow GPIO3 to be driven as AXIS reset (GPIO2 and GPIO3 interrupts are automatically disabled and outputs inhibited) 0 = Do not drive clock onto GPIO2;...

  • Page 66: Timer 0 Control And Status Register 2 (0X651) And Timer 1 Control And Status Register 2 (0X659)

    6.17 Timer 0 Control and Status Register 2 (0x651) and Timer 1 Control and Status Register 2 (0x659) Bits Read/Write Description Default 7 to 5 Read only Reserved Read/Write Timer read latch select: 1 = Latch all timers on read of timer 0 LSB 0 = Latch individual timers on read of individual timer LSB 3 and 2 Read only...

  • Page 67: Writes

    6.19.2 Writes Writes always update the timer load value, irrespective of the setting of bit 3 of the Timer 0 Control and Status Register 1. Register Name Timer Bits 0x654 Timer 0 Data Byte 0 (least significant byte) 7 to 0 0x655 Timer 0 Data Byte 1 8 to 15...

  • Page 68: Gpio In Register (0X671)

    6.22 GPIO In Register (0x671) This returns the status of the GPIO pins, regardless of the direction mode. Bits Read/Write Description Default 7 to 0 Read/Write GPIO7 to GPIO0 respectively 0x00 6.23 GPIO Direction Register (0x672) Bits Read/Write Description Default 7 to 0 Read/Write GPIO7 to GPIO0 respectively: 0x00...

  • Page 69: Gpio Both Edges Register (0X676)

    6.27 GPIO Both Edges Register (0x676) When enabled, both-edge mode causes interrupts to be generated on both rising and falling edges. The GPIO bit must be in edge mode for both-edge mode to work. Bits Read/Write Description Default 7 to 0 Read/Write GPIO7 to GPIO0 respectively: 0x00 1 = Both-edge mode enabled...

  • Page 70: Gpio15 To Gpio8 Availability Register (0X684)

    6.30 GPIO15 to GPIO8 Availability Register (0x684) As GPIO15 to GPIO8 are not supported on SBC347A, this register returns 0x00. 6.31 VPX GDISCRETE1 Out Register (0x688) The value of this register is driven onto the GDISCRETE1 pin when the direction mode is set to output: Bits Read/Write...

  • Page 71: Vpx Gdiscrete1 Active Low/High Register (0X68D)

    6.36 VPX GDISCRETE1 Active Low/High Register (0x68D) This sets the interrupt detection sensitivity of the GDISCRETE1 pin (active high/ low or rising/falling edge depending on sensitivity mode): Bits Read/Write Description Default Read/Write GDISCRETE1: 1 = Active high/rising edge 0 = Active low/falling edge Depending on whether the bit is in level or edge mode 6 to 0 Read only...

  • Page 72: Ethernet Port Availability Register (0X6A0)

    6.40 Ethernet Port Availability Register (0x6A0) NOTE Even when a port is not available due to a build option, it may still be visible to software. Bits Description Default 7 to 2 Ethernet ports 7 to 2. 000000 Ethernet port 1 availability: 0 = Ethernet port 1 is not available 1 = Ethernet port 1 is available Ethernet port 0 availability:...

  • Page 73: Com Port Modem Configuration Register (0X6A3)

    6.43 COM Port Modem Configuration Register (0x6A3) Bits Description Default 7 to 2 Reserved 000000 COM2 modem configuration: Modem signal support is not available. 0 =Full modem line support is not available COM1 modem configuration: Modem signal support is not available. 0 =Full modem line support is not available 6.44 SATA Port Availability Register (0x6A4) Availability of SATA ports 1 and 2 is build option dependent.

  • Page 74: Usb3.0 Port Availability Register (0X6A6)

    6.46 USB3.0 Port Availability Register (0x6A6) As the SBC347A has no USB3.0 ports, this returns 0x00. 6.47 USB2.0 Port 15 to 8 Availability Register (0x6A7) As USB2.0 ports 15 to 8 are not available, this returns 0x00. 6.48 USB3.0 Port 15 to 8 Availability Register (0x6A8) As USB3.0 ports 15 to 8 are not available, this returns 0x00.

  • Page 75: Ancillary/Audio Availability Register (0X6Ad)

    6.53 Ancillary/Audio Availability Register (0x6AD) Availability of audio signals is build option dependent. Bits Description Default Front panel I/O availability: Front panel I/O is not available. 0 = Front panel I/O not available 6 to 1 Reserved 000000 Audio is not available 6.54 Front Panel Configuration Register (0x6AE) As no front panel I/O is present on the SBC347A, this returns 0x00.

  • Page 76: Ssd Secure Hardware Erase Capability Register (0X6B2)

    6.56 SSD Secure Hardware Erase Capability Register (0x6B2) Hardware Secure Erase is not currently available, but may be in the future. When available, triggering a hardware erase function will result in a secure erase algorithm being executed. Bits Description Default 7 to 1 SSD7 to SSD1 availability: 0000000...

  • Page 77: Com Port Mode Register (0X6Bc)

    6.59 COM Port Mode Register (0x6BC) Bits Read/Write Description Default 7 to 2 Read only COM8 to COM3 mode: 000000 COM8 to COM3 are not available Read/Write COM2 mode: 1 = COM2 transceiver in RS422 mode 0 = COM2 transceiver in RS232 mode Read/Write COM1 mode: 1 = COM1 transceiver in RS422 mode 0 = COM1 transceiver in RS232 mode...

  • Page 78: Ssd Erase Control Register (0X6Bf)

    6.62 SSD Erase Control Register (0x6BF) To trigger a hardware erase, bit 0 must be written with a ‘1’, ‘0’, ‘1’ pattern on consecutive write cycles to this register. This is to protect against ‘accidental’ erase functions. The value read from this register represents the state of the output, not the last value written.

  • Page 79: Test Register (0X6C7)

    6.66 Test Register (0x6C7) Bits Description Default 7 to 1 Reserved 0000000 CPU daisy-chain status: 1 = Chain fault 0 = Chain OK 6.67 Backplane Status Register (0x6CA) This register inverts the Geographic Addressing (GA) bits so that software can read a true slot number, e.g., the SBC347A in slot 1 (only GA0 pulled low) results in bits 4 to 0 reading 00001 Bits...

  • Page 80: Write Protection Status Register (0X6Cc)

    6.69 Write Protection Status Register (0x6CC) Bit Description Default Reserved Ethernet controller configuration FLASH write protection status 1 = Hardware write protection is active 0 = Hardware write protection is not active SPD EEPROM write protection status 1 = Write protection is active 0 = Write protection is not active Reserved Boot SPI FLASH (main) write protection status...

  • Page 81: Boot Location Status Register (0X6Ce)

    6.71 Boot Location Status Register (0x6CE) Bits Description Default Auto swap failover 0 = SBC347A booted normally 6 and 5 Active boot ROM location 1x = Active boot ROM is located on the test card (factory only) 00 = Active boot ROM is the Main onboard ROM 01 = Active boot ROM is the Recovery onboard ROM SPD location 1 = SBC347A booted using SPD EEPROM(s) located on the TAC...

  • Page 82: Connectors

    7 • Connectors The following table shows the function of the connectors on the SBC347A: Table 7-1 Connector Functions Connector Function P0 to P2 VPX interface P5 (on rear of PWB) TAC connector Figure 7-1 Front Connector Positions and Numbering NOTE The SBC347A’s guide pin receptacles are unkeyed by default, but may be keyed to customer requirements.

  • Page 83: Backplane Connectors (Vpx)

    7.1 Backplane Connectors (VPX) The following sections show the pin assignments of the SBC347A VPX backplane connectors (P0 to P2). These are shown in the 7-row format as used in the VPX specifications. Also provided are the corresponding pinouts for the J0 to J2 backplane connectors.

  • Page 84: P1 Pin Assignments (I/O Product Option E = 0)

    7.1.3 P1 Pin Assignments (I/O Product Option E = 0) Table 7-4 P1 Pin Assignments COM2_RTS VBAT PEG_RXP0 PEG_RXN0 PEG_TXP0 PEG_TXN0 SYS_CON# PEG_RXP1 PEG_RXN1 PEG_TXP1 PEG_TXN1 PEG_RXP2 PEG_RXN2 PEG_TXP2 PEG_TXN2 COM2_CTS PEG_RXP3 PEG_RXN3 PEG_TXP3 PEG_TXN3 SATA0_RXP SATA0_RXN SATA0_TXP SATA0_TXN COM1_TXD USB_P0_P USB_P0_N USB_P1_P...

  • Page 85: J1 Pinout (I/O Product Option E = 0)

    7.1.4 J1 Pinout (I/O Product Option E = 0) Table 7-5 J1 Pin Assignments COM2_RTS VBAT PEG_RXP0 PEG_RXN0 PEG_TXP0 PEG_TXN0 SYS_CON# PEG_RXP1 PEG_RXN1 PEG_TXP1 PEG_TXN1 PEG_RXP2 PEG_RXN2 PEG_TXP2 PEG_TXN2 COM2_CTS PEG_RXP3 PEG_RXN3 PEG_TXP3 PEG_TXN3 SATA0_RXP SATA0_RXN SATA0_TXP SATA0_TXN COM1_TXD USB_P0_P USB_P0_N USB_P1_P USB_P1_N...

  • Page 86: P2 Pin Assignments (I/O Product Option E = 0)

    7.1.5 P2 Pin Assignments (I/O Product Option E = 0) Table 7-6 P2 Pin Assignments PEG_RXP4 PEG_RXN4 PEG_TXP4 PEG_TXN4 PEG_RXP5 PEG_RXN5 PEG_TXP5 PEG_TXN5 PEG_RXP6 PEG_RXN6 PEG_TXP6 PEG_TXN6 COM1_RTS PEG_RXP7 PEG_RXN7 PEG_TXP7 PEG_TXN7 DP01_RXP0 DP01_RXN0 DP01_TXP0 DP01_TXN0 COM1_CTS DP01_RXP1 DP01_RXN1 DP01_TXP1 DP01_TXN1 DP01_RXP2 DP01_RXN2...

  • Page 87: J2 Pinout (I/O Product Option E = 0)

    7.1.6 J2 Pinout (I/O Product Option E = 0) Table 7-7 J2 Pin Assignments PEG_RXP4 PEG_RXN4 PEG_TXP4 PEG_TXN4 PEG_RXP5 PEG_RXN5 PEG_TXP5 PEG_TXN5 PEG_RXP6 PEG_RXN6 PEG_TXP6 PEG_TXN6 COM1_RTS PEG_RXP7 PEG_RXN7 PEG_TXP7 PEG_TXN7 DP01_RXP0 DP01_RXN0 DP01_TXP0 DP01_TXN0 COM1_CTS DP01_RXP1 DP01_RXN1 DP01_TXP1 DP01_TXN1 DP01_RXP2 DP01_RXN2 DP01_TXP2...

  • Page 88: P1 Pin Assignments (I/O Product Option E = 1)

    7.1.7 P1 Pin Assignments (I/O Product Option E = 1) Table 7-8 P1 Pin Assignments DP00_RXP0 DP00_RXN0 DP00_TXP0 DP00_TXN0 COM2_RTS DP00_RXP1 DP00_RXN1 DP00_TXP1 DP00_TXN1 GPIO0 GPIO1 GPIO4 GPIO5 VBAT GPIO2 GPIO3 GPIO6 GPIO7 PEG_RXP0 PEG_RXN0 PEG_TXP0 PEG_TXN0 SYS_CON# PEG_RXP1 PEG_RXN1 PEG_TXP1 PEG_TXN1 PEG_RXP2...

  • Page 89: Backplane J1 Pinout (I/O Product Option E = 1)

    7.1.8 Backplane J1 Pinout (I/O Product Option E = 1) Table 7-9 J1 Pin Assignments DP00_RXP0 DP00_RXN0 DP00_TXP0 DP00_TXN0 COM2_RTS DP00_RXP1 DP00_RXN1 DP00_TXP1 DP00_TXN1 GPIO0 GPIO1 GPIO4 GPIO5 VBAT GPIO2 GPIO3 GPIO6 GPIO7 PEG_RXP0 PEG_RXN0 PEG_TXP0 PEG_TXN0 SYS_CON# PEG_RXP1 PEG_RXN1 PEG_TXP1 PEG_TXN1 PEG_RXP2...

  • Page 90: P2 Pin Assignments (I/O Product Option E = 1)

    7.1.9 P2 Pin Assignments (I/O Product Option E = 1) Table 7-10 P2 Pin Assignments PEG_RXP4 PEG_RXN4 PEG_TXP4 PEG_TXN4 PEG_RXP5 PEG_RXN5 PEG_TXP5 PEG_TXN5 PEG_RXP6 PEG_RXN6 PEG_TXP6 PEG_TXN6 COM1_RTS PEG_RXP7 PEG_RXN7 PEG_TXP7 PEG_TXN7 DP01_RXP0 DP01_RXN0 DP01_TXP0 DP01_TXN0 COM1_CTS DP01_RXP1 DP01_RXN1 DP01_TXP1 DP01_TXN1 DP01_RXP2 DP01_RXN2...

  • Page 91: Backplane J2 Pinout (I/O Product Option E = 1)

    7.1.10 Backplane J2 Pinout (I/O Product Option E = 1) Table 7-11 J2 Pin Assignments PEG_RXP4 PEG_RXN4 PEG_TXP4 PEG_TXN4 PEG_RXP5 PEG_RXN5 PEG_TXP5 PEG_TXN5 PEG_RXP6 PEG_RXN6 PEG_TXP6 PEG_TXN6 COM1_RTS PEG_RXP7 PEG_RXN7 PEG_TXP7 PEG_TXN7 DP01_RXP0 DP01_RXN0 DP01_TXP0 DP01_TXN0 COM1_CTS DP01_RXP1 DP01_RXN1 DP01_TXP1 DP01_TXN1 DP01_RXP2 DP01_RXN2...

  • Page 92: Signal Descriptions

    7.1.11 Signal Descriptions Table 7-12 Backplane Connector Signal Descriptions Name Description VS2, VS3 VPX Vs2 (+3.3 V) and Vs3 (+5 V) power inputs. See Section A.2 "Electrical Specification" page 96 more details. P3V3_AUX VPX +3.3 V DC auxiliary power input. See Section A.2 "Electrical Specification"...

  • Page 93: Figure 7-3 Rs422/485 Signal Definition

    Table 7-12 Backplane Connector Signal Descriptions (Continued) Name Description SYS_CON~ Pulled low by the backplane to indicate that the board is the VPX System Controller. The state is shown in the FPGA Backplane Status Register (0x6CA). MASKABLE_RST~ OpenVPX Maskable Reset signal. Pulling this input low for a minimum of 10 ms will cause a hard reset to the SBC347A unless it is masked (unmasked by default).

  • Page 94: P5 Connector (Tac)

    7.2 P5 Connector (TAC) This 80-way Molex connector (where fitted) is for Factory/Field Application Engineer use only. It provides an interface between the TAC and onboard programmable devices. The pinout for the TAC connector is for Factory use only. 94 SBC347A 3U VPX Single Board Computer Publication No.

  • Page 95: A • Specifications

    A • Specifications A.1 Technical Specification Table A-1 Technical Data Features Details Comments Processor 5th Generation Core i7 dual/quad core Various Intel SKUs supported Up to 16 GBytes DDR3 SDRAM with ECC Dual memory controllers running at 1600 MHz data rate NVRAM 512 KBytes FRAM Nonvolatile storage for data that must not be lost when...

  • Page 96: Electrical Specification

    A.2 Electrical Specification A.2.1 Voltage Supply Requirements The SBC347A requires Vs2 (+3.3 V), Vs3 (+5 V), and 3V3_AUX supplies. These must remain within the limits specified below. If either of the supplies is outside of these specifications at powerup, the SBC347A will fail to start. If the supplies fall outside of these limits during a powered state, the SBC347A is held in reset and all onboard supplies are shut down.

  • Page 97: 3.3 V Auxiliary Supply

    This power was measured under the following conditions: Table A-5 Power Measurement Conditions Operation Hardware Connections Software Typical Windows 7 - idle 10 GbE x2 (linked @ 10GBASE-T) Proprietary test software (running under Windows 7) configured COM1 serial port Maximum to exercise all main functional blocks simultaneously.

  • Page 98: Reliability (Mtbf)

    A.4 Reliability (MTBF) The following table shows the predicted values for reliability as Mean Time Between Failures (MTBF) and failures per million hours (fpmh) for the SBC347A-x413U4xx (see Section A.6 ʺProduct Codesʺ page 100 for variant codes) as of 12th September 2013. Table A-9 Reliability (MTBF) Environment Temp...

  • Page 99: Environmental Specifications

    A.5 Environmental Specifications For details of Abaco’s approach to full environmental compliance and a description of the Build Levels referred to below, please see the Ruggedization Levels located at the following links. LINKS https://www.abaco.com/rugged-systems https://www.abaco.com/download/ruggedization-levels A.5.1 Convection-cooled Boards Table A-10 Convection-cooled Environmental Specifications Build Style Temperature (°C) Vibration...

  • Page 100: Product Codes

    A.6 Product Codes Table A-12 Product Options SBC347A- A 1 = 0.8" pitch, VITA 46 mechanics 6 = 1" pitch, VITA 48 mechanics 0 = Reserved 0 = BIOS only 1 = BIOS + BIT 3 = BIOS + VxWorks 4 = BIOS + BIT + VxWorks 0 = SBC325W09 (no XMC) compatible I/O 1 = Full I/O Routed (GPIO, DVI, additional x2 PCIe, x4 PCIe and...

  • Page 101: Software Support

    A.7 Software Support Abaco’s software strategy allows fully integrated system-level solutions to be realized easily and with confidence. Off-the-shelf, layered software modules deliver the most from low-level hardware features while exploiting the best high level debug and run-time functionality of popular commercial off-the-shelf (COTS) operating systems and communications modules.

  • Page 102: I/O Modules

    A.8 I/O Modules The SBC347A can be used with the SBC346ARTM, depending on the development system being used. NOTE The RTM contains PCIe redrivers that are limited to Gen2. When using the SBC347A with the SBC346ARTM, the user must ensure that the PEG Port 0 is set to Gen1 or Gen2 in the BIOS setup. When using an Abaco SCVPX3U-12 starter chassis, the SBC346RTM is required.

  • Page 103: B • Statement Of Volatility

    B • Statement of Volatility B.1 Volatile Memory The SBC347A contains volatile memory, i.e., memory in which the contents are lost when power is removed. None of this volatile memory is capable of write protection. Table B-1 Volatile Memory User User Data Memory Type Size...

  • Page 104: Nonvolatile Memory

    B.2 Nonvolatile Memory The SBC347A contains nonvolatile memory, i.e., memory in which the contents are retained when power is removed. Table B-2 Nonvolatile Memory User User Data Write Memory Type Size Function Process to Clear Modifiable? Access? Protectable? SATA NAND 32-GByte Solid State Flash drive stores Any hard drive formatting...

  • Page 105: C • Thermal Derating

    C • Thermal Derating The processor speed and the temperature are inter-dependent. This means that for a given temperature, a maximum processor speed is achievable before throttling, and conversely for a given processor speed before throttling, a maximum temperature is achievable. This is further affected by the build level, which dictates the maximum ambient temperature at which the board can operate (see Section A.5 ʺEnvironmental Specificationsʺ...

  • Page 106: Glossary

    Glossary NOTE The connector signals are explained in Section 7.1.11 "Signal Descriptions" page APIC Advanced Programmable Interrupt Controller Advanced Vector Extensions AXIS Advanced Multiprocessor Integrated Software Background Condition Screening Built-in-test Board Management Microcontroller COTS Commercial Off-the-shelf DIMM Dual Inline Memory Module Digital Signal Processor Data Terminal Equipment Error Checking and Correction...
  • Page 107 Over-current Protection Printed Circuit Board Peripheral Controller Hub PCIe PCI Express PCI Express Graphics Programmable Interrupt Controller POST Power On Self Test Power Supply Unit Printed Wiring Board Rivest, Shamir, and Aldeman Real Time Clock Rear Transition Module Ready to Send Single Board Computer Stock Keep Unit Single Level Cell...

  • Page 108: Index

    Index P2 ..............90 P5 ................94 Abaco Documents ............4 Positions and Numbering ........82 Abaco Website ..............4 Signal Descriptions ..........92 Air-cooled ............16, 59, 99 TAC ................94 Airflow ................16 Convection-cooled ............99 Auxiliary Supply ............97 Cooling ..............
  • Page 109 I2C Bus ................47 Inspection ............... 20 Real Time Clock ............46 Interrupt Controllers ............. 57 Recovery Boot ..............20 Introduction ..............14 Registers ................. 60 Ancillary/Audio Availability ....... 75 AXIS Clock Control ..........65 AXIS Clock Frequency .......... 65 JTAG ................
  • Page 110 UART Enable ............76 USB2.0 Port 15 to 8 Availability ......74 USB ................. 41 USB2.0 Port Availability ........73 USB3.0 Port 15 to 8 Availability ......74 USB3.0 Port Availability ........74 Vibration ................ 99 VGA Display Availability ........74 Video ................
  • Page 111 © 2016 Abaco Systems, Inc. All rights reserved. Information Centers For more information, please visit the * indicates a trademark of Abaco Systems, Inc. and/or its affiliates. All other Abaco Systems website at: Americas: trademarks are the property of their 1-866-652-2226 (866-OK-ABACO) respective owners.

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