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For U.S.A., Canada, Europe, China & Japan model SERVICE MANUAL PMD620 MODEL Handheld Solid State Recorder LEVEL OVER STOP/CANCEL REC PAUSE DISPLAY MENU/STORE ENTER SKIP BACK PMD620 SOLID STATE RECORDER Please use this service manual with referring to the user guide ( D.F.U. ) without fail.
1. TECHNICAL SPECIFICATIONS Digital Audio System General System ..........Solid State Recorder Power consumption Usable media ..........SD/SDHC cards Recording/Playback .........1.5 W (DC) Recording format Battery life (Alkaline) ....... 5 hours (Typical) MP3 ........MPEG1 Layer III Compression Phantom power ......... 5V, 1mA (Max.) WAV ..........
2. SERVICE メニュー 2. SERVICE MENU <Service Menu Details> <サービスメニューの内容> Display Menu Service Details 表示メニュー サービス内容 Check the display section by lighting all OLED. 1 OLED Check OLED の全点灯により、 表示部を確認します。 Check the LED by lighting all LED. 2 LED Check LED の全点灯により、...
ON を選択します。このとき、 選択したメニューがハイ ライト表示されます。 At this time, the selected menu item is highlighted. 3) 3 / 8 /ENTER ボ タ ン を 押 す と、 PMD620 を セ ン サ OFF 3) If the 3/8/ENTER button is pressed, the PMD620 sensor 状態に設定します。...
2.4 Heat Run 2.4 ヒートラン実行 1) Press the REC PAUSE button and REC LEVEL – button 1) REC PAUSE ボタンと REC LEVEL − ボタンを同 時に at the same time, and turn the POWER slide switch ON. 押しながら、 POWER slide スイッチを On します。この At this time, the service menu list is displayed in the とき、...
3. 分解方法 3. HOW TO DISASSEMBLE 1) Open the battery cover on the back of the main unit, and 1) 本体背面のバッテリーカバーを開き、 ネジ A 4 本を外し remove the 4 “A” screws. ます。 Battery cover 2) Lift the rear block slowly in the direction of the arrows, 2) リアブロックをゆっくり矢印の方向へ持ち上げ、...
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3) 下図のように Mic Rch ケーブル w のコネクタを J608 か 3) As shown in the diagram below, disconnect the Mic Rch cable 2 connector from J608, the Mic Lch cable ら外し、 Mic Lch ケーブルeのコネクタをJ607から外し、 3 connector from J607, and the Mic shield cable r Mic シールドケーブル...
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4) Lift the P102 jack section, and remove the P102 board 4) P102 のジャック部分を持ち上げてバッテリブロックか from the battery block in the direction of the arrow. Also, ら P102 基板を矢印方向に取り外します。またジャック the jack side block can be removed. The battery block サイドブロックも取り外せます。USB キャップの足で is held in place by the foot of the USB cap.
4. SD カードからのバージョンアップ方法 4. Version Update 1) アップデート用の SD カードを本体の挿入口に差し込み 1) Insert the SD card for updating into the loading slot of the ます。 main unit. 2) POWER slide スイッチを On します。このとき、 表示部 2) Turn the POWER slide switch ON. At this time, “Update に...
5. BLOCK DIAGRAM U S B V B U S 5V V I N Q614 POW SW Q201 D201∼D206 S703 S704 Q203,204 Q083 S-IN P-OUT POWER KEY LOCK LED DRIVER VIN _LOW BATTERY SHIFT REC/LEVEL/PEAK _DET AA or RESISTER NIMH Q615,D61 X2...
9. IC DATA Q001 : TMS320VC5509AZHH 179-TERMINAL GHH AND ZHH BALL GRID ARRAY (BOTTOM VIEW) 10 11 12 13 BLOCK DIAGRAM USB PLL † † † † Number of pins determined by package type.
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Q001 : TMS320VC5509AZHH PIN ASSIGNMENTS FOR THE GHH AND ZHH PACKAGES SIGNAL SIGNAL SIGNAL BALL # SIGNAL NAME BALL # BALL # BALL # NAME NAME NAME V SS GPIO5 DV DD GPIO4 CV DD DV DD FSR0 CV DD DV DD DV DD V SS...
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Q005 : MT48LC4M16A2B4-7E BLOCK DIAGRAM CONTROL LOGIC BANK3 CAS# BANK2 BANK1 RAS# REFRESH MODE REGISTER COUNTER BANK0 ROW- ADDRESS ROW- BANK0 ADDRESS MEMORY 4096 LATCH ARRAY & (4,096 x 1,024 x 4) DECODER DATA SENSE AMPLIFIERS OUTPUT REGISTER 4096 I/O GATING DQ0–DQ3 DQM MASK LOGIC BANK...
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Q005 : MT48LC4M16A2B4-7E PIN/BALL DESCRIPTIONS VFBGA Ball Numbers Symbol Type Description Input Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on the positive edge of CLK. CLK also increments the internal burst counter and controls the output registers. Input Clock enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal.
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Q006 : S29AL016D70BFI020 BLOCK DIAGRAM – DQ15 (A-1) RY/BY# Sector Switches Erase Voltage Input/Output RESET# Generator Buffers State Control BYTE# Command Register PGM Voltage Generator Data Chip Enable Latch Output Enable Logic Y-Decoder Y-Gating Detector Timer Cell Matrix X-Decoder A0–A19 CONNECTION DIAGRAMS FBGA Top View, Balls Facing Down...
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Q006 : S29AL016D70BFI020 PIN CONFIGURATION A0–A19 20 addresses DQ0–DQ14 15 data inputs/outputs DQ15/A-1 DQ15 (data input/output, word mode), A-1 (LSB address input, byte mode) BYTE# Selects 8-bit or 16-bit mode Chip enable Output enable Write enable RESET# Hardware reset pin RY/BY# Ready/Busy output 3.0 volt-only single power supply...
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Q083 : NJU7700-F4/F15 1. V 2. V 3. NC 4. V VREF...
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Q201 : NJU3713A Package Outline PIN CONFIGURATION SSOP20 DATA BLOCK DIAGRAM DATA Controller Circuit TERMINAL DESCRIPTION SYMBOL FUNCTION Parallel Conversion Data Output Terminals Non Connection Parallel Conversion Data Output Terminals DATA Serial Data Input Terminal Clock Signal Input Terminal Strobe Signal Input Terminal Clear Signal Input Terminal Non Connection Parallel Conversion Data Output Terminals...
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Q202 : NJU3754 Package Outline PIN CONFIGURATION SSOP16 BLOCK DIAGRAM Control Circuit TERMINAL DESCRIPTION SYMBOL FUNCTION Parallel Data Input Terminals (with pull-up resistors) Ground Parallel Data Input Terminals (with pull-up resistors) Serial Data Output Terminal Serial Clock Input Terminal Chip Enable Input Terminal Power Supply Terminal (2.7 to 5.5V)
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Q207 : M66592FP PIN LAYOUT DIAGRAM D6/AD6 INT_N D5/AD5 SOF_N D4/AD4 RD_N M66592FP D3/AD3 WR0_N D2/AD2 WR1_N D1/AD1 CS_N DREQ0_N (TOP VIEW) A6/ ALE DACK0_N DEND0_N DREQ1_N DACK1_N/DSTB0_N DEND1_N RST_N MPBUS *The “_N” in the signal name Package indicates that the signal is in M66592FP : 64pinLQFP (0.5mm pitch) the “L”...
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Q207 : M66592FP PIN DESCRIPTIONS Category Pin name Name Function State of pin *7) count RST_N=” RST_N PCUT=1 (Pin nos.) L” goes “H” CPU bus D15-0 Data Bus This is a 16-bit data bus. 24-39 Input interface (Hi-z) AD6-1 Multiplex When a multiplex bus is specified, this Address Bus group of pins is used on a time-shared...
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Category Pin name Name Function State of pin *7) count RST_N=” RST_N PCUT=1 (Pin nos.) L” goes “H” System RST_N Reset signal At “L” level, the controller is initialized. Input Input Input control TEST Test signal This should be fixed at “L” or open. USB bus USB D+ data This should be connected to the D+ pin of...
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Q207 : M66592FP PIN FUNCTION CONFIGURATION DIAGRAM CPU bus interface D15-7,D6-1(/AD6-1),D0 A6/ALE,A5-1 CS_N RD_N WR0_N WR1_N MPBUS Interrupt / SOF output INT_N SOF_N Clock M66592 XOUT DMA interface VBUS monitor input DREQ0_N VBUS DACK0_N DEND0_N DREQ1_N DACK1_N/DSTB0_N DEND1_N Split bus USB interface DP, DM SD7-0...
Q304, Q604 : LTC3400BES6 TOP VIEW SW 1 GND 2 FB 3 4 SHDN S6 PACKAGE 6-LEAD PLASTIC SOT-23 BLOCK DIAGRAM 4.7μH SINGLE CELL 1μF OPTIONAL INPUT SCHOTTKY GOOD 2.3V START-UP 3.3V OUTPUT 0.45Ω SYNC DRIVE CONTROL 0.35Ω CONTROL 1.02M RAMP Σ...
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Q311 : S-35390A-I8T1G SNT-8A (TOP VIEW) INT1 XOUT INT2 PIN DESCRIPTION Pin No. Symbol Description Configuration Interrupt 1 signal output pin Nch open-drain output (no Depending on the mode set by INT1 register_1 protective diode on the side and the status register, it outputs low or a clock of VDD) INT1 when the time is reached.
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Q405 : ADG736 PIN CONFIGURATION (10-Lead µSOIG) ADG736 TOP VIEW (Not to Scale) Truth Table Logic Switch A Switch B BLOCK DIAGRAM ADG736 SWITCHES SHOWN FOR A LOGIC "1" INPUT...
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Q412 : TLV320AIC32 TERMINAL FUNCTIONS TERMINAL DESCRIPTION NAME QFN NO. MCLK Master clock input BCLK Audio serial data bus bit clock input/output WCLK Audio serial data bus word clock input/output Audio serial data bus data input DOUT Audio serial data bus data output DVSS Digital core / I/O Ground Supply, 0 V IOVDD...
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Q302 : XC6210B152M, Q303 : XC6210B122M, Q607 : XC6210B182M, Q415 : XC6210B452M VOUT VIN VSS CE SOT-25 (TOP VIEW) PIN ASSIGNMENT PIN NUMBER PIN NAME FUNCTION SOT-25 ON/OFF Control Power Input Ground Output No Connection BLOCK DIAGRAM...
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Q608 : XC6210B332P VOUT SOT-89-5 (TOP VIEW) PIN ASSIGNMENT PIN NUMBER PIN NAME FUNCTION SOT-89-5 ON/OFF Control Power Input Ground Output No Connection BLOCK DIAGRAM...