Renesas REJ06B0732-0100 Application Note page 6

2.2 Operational Description of Sample Program
The settings of the DMAC for the sample program are listed in table 4. Also, the operation of the sample program is
illustrated in figure 4.
Table 4 Settings of DMAC
DMA transfer condition
Channel
Length of transfer data
Maximum transfer count
Address mode
Bus mode
Priority level
Interrupt request
DMAC
SAR
DAR
[Legend]
SAR:Source address register
DAR:Destination address register
REJ06B0732-0100/Rev.1.00
Data Transfer between On-chip RAM Areas with DMAC (Cycle-Stealing Mode)
Auto request mode
CH0
4 bytes
128 transfers (128 × data length of 4 bytes = 512-byte data)
Dual address mode
Cycle-stealing mode
Channel priority level fixed mode
Disable an interrupt request to the CPU at the end of a transfer
Transfer source
address
Transfer
destination
address
Figure 4 Operation of Sample Program
March 2008
On-chip RAM
H'0xFFF81000
512-byte data
H'0xFFF82000
512-byte data
SH7211 Group
DMA transfer
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