Marantz PMD671 Service Manual page 43

QD01 : TMS320VC5416PGE-160
The TMS320VC5416PGE 144-pin low-profile quad flatpack (LQFP) pin assignments are sh
Figure 2–2.
CV SS
1
A22
2
CV SS
3
DV DD
4
A10
5
HD7
6
A11
7
A12
8
A13
9
A14
10
A15
11
CV DD
12
HAS
13
DV SS
14
CV SS
15
CV DD
16
HCS
17
HR/W
18
READY
19
PS
20
DS
21
IS
22
R/W
23
MSTRB
24
IOSTRB
25
MSC
26
XF
27
HOLDA
28
IAQ
29
HOLD
30
BIO
31
MP/MC
32
DV DD
33
CV SS
34
BDR1
35
BFSR1
36
Signal Descriptions
Table 2–2 lists each signal, function, and operating mode(s) grouped by function. See Section 2.2 for exact
pin locations based on package type.
Table 2–2. Signal Descriptions
TERMINAL TERMINAL
I/O † I/O †
DESCRIPTION DESCRIPTION
NAME
DATA SIGNALS
I/O/Z ‡§
A22 (MSB) Parallel address bus A22 [most significant bit (MSB)] through A0 [least significant bit (LSB)]. The sixteen LSB
A21 lines, A0 to A15, are multiplexed to address external memory (program, data) or I/O. The seven MSB lines, A16
A20 to A22, address external program space memory. A22–A0 is placed in the high-impedance state in the hold
A19 mode. A22–A0 also goes into the high-impedance state when OFF is low.
A18
A17 A17–A0 are inputs in HPI16 mode. These pins can be used to address internal memory via the host-port interface
A16 (HPI) when the HPI16 pin is high. These pins also have Schmitt trigger inputs.
A15
A14 The address bus has a bus holder feature that eliminates passive components and the power dissipation
A13 associated with them. The bus holder keeps the address bus at the previous logic level when the bus goes into
A12 a high-impedance state.
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0 (LSB)
I/O/Z ‡§
D15 (MSB) Parallel data bus D15 (MSB) through D0 (LSB). D15–D0 is multiplexed to transfer data between the core CPU
D14 and external data/program memory or I/O devices or HPI in HPI16 mode (when HPI16 pin is high). D15–D0 is
D13 placed in the high-impedance state when not outputting data or when RS or HOLD is asserted. D15–D0 also goes
D12 into the high-impedance state when OFF is low. These pins also have Schmitt trigger inputs.
D11
D10 The data bus has a bus holder feature that eliminates passive components and the power dissipation associated
D9 with them. The bus holder keeps the data bus at the previous logic level when the bus goes into the
D8 high-impedance state. The bus holders on the data bus can be enabled/disabled under software control.
D7
D6
D5
D4
D3
D2
D1
D0 (LSB)
† I = Input, O = Output, Z = High-impedance, S = Supply
‡ These pins have Schmitt trigger inputs.
§ This pin has an internal bus holder controlled by way of the BSCR register.
¶ This pin has an internal pullup resistor.
# This pin has an internal pulldown resistor.
Table 2–2. Signal Descriptions (Continued)
TERMINAL TERMINAL
I/O † I/O †
NAME NAME
INITIALIZATION, INTERRUPT AND RESET OPERATIONS
Interrupt acknowledge signal. IACK indicates receipt of an interrupt and that the program counter is fetching the
IACK O/Z
interrupt vector location designated by A15–A0. IACK also goes into the high-impedance state when OFF is low.
INT0 ‡
INT1 ‡
External user interrupt inputs. INT0–INT3 are maskable and are prioritized by the interrupt mask register (IMR)
I
INT2 ‡
and the interrupt mode bit. INT0 –INT3 can be polled and reset by way of the interrupt flag register (IFR).
INT3 ‡
A18
108
Nonmaskable interrupt. NMI is an external interrupt that cannot be masked by way of the INTM or the IMR. When
A17
107 NMI ‡ I
NMI is activated, the processor traps to the appropriate vector location.
DV SS
106
A16
105
Reset. RS causes the digital signal processor (DSP) to terminate execution and forces the program counter to
D5
104 RS ‡ I
0FF80h. When RS is brought to a high level, execution begins at location 0FF80h of program memory. RS affects
D4
103 various registers and status bits.
D3
102
Microprocessor/microcomputer mode select. If active low at reset, microcomputer mode is selected, and the
D2
101
internal program ROM is mapped into the upper 16K words of program memory space. If the pin is driven high
D1
100
MP/MC I during reset, microprocessor mode is selected, and the on-chip ROM is removed from program space. This pin
D0
99
is only sampled at reset, and the MP/MC bit of the processor mode status (PMST) register can override the mode
RS
98
that is selected at reset.
X2/CLKIN
97
X1
96 MULTIPROCESSING SIGNALS
95 HD3
Branch control. A branch can be conditionally executed when BIO is active. If low, the processor executes the
94 CLKOUT
BIO ‡
I conditional instruction. The BIO condition is sampled during the decode phase of the pipeline for the XC
93 DV SS
instruction, and all other instructions sample BIO during the read phase of the pipeline.
92 HPIENA
91 CV DD
External flag output (latched software-programmable signal). XF is set high by the SSBX XF instruction, set low
90 CV SS
by RSBX XF instruction or by loading ST1. XF is used for signaling other processors in multiprocessor
XF O/Z
89 TMS
configurations or used as a general-purpose output pin. XF goes into the high-impedance state when OFF is low,
88 TCK
and is set high at reset.
87 TRST
MEMORY CONTROL SIGNALS
86 TDI
85 TDO
Data, program, and I/O space select signals. DS, PS, and IS are always high unless driven low for
DS
84 EMU1/OFF
communicating to a particular external space. Active period corresponds to valid address information. DS, PS,
PS O/Z
83 EMU0
and IS are placed into the high-impedance state in the hold mode; these signals also go into the high-impedance
IS
82 TOUT
state when OFF is low.
81 HD2
Memory strobe signal. MSTRB is always high unless low-level asserted to indicate an external bus access to
80 HPI16
MSTRB O/Z data or program memory. MSTRB is placed in the high-impedance state in the hold mode; it also goes into the
79 CLKMD3
high-impedance state when OFF is low.
78 CLKMD2
77 CLKMD1 Data ready. READY indicates that an external device is prepared for a bus transaction to be completed. If the
76 DV SS device is not ready (READY is low), the processor waits one cycle and checks READY again. Note that the
READY I
75 DV DD processor performs ready detection if at least two software wait states are programmed. The READY signal is
74 BDX1 not sampled until the completion of the software wait states.
73 BFSX1
Read/write signal. R/W indicates transfer direction during communication to an external device. R/W is normally
R/W O/Z in the read mode (high), unless it is asserted low when the DSP performs a write operation. R/W is placed in the
high-impedance state in the hold mode; and it also goes into the high-impedance state when OFF is low.
I/O strobe signal. IOSTRB is always high unless low-level asserted to indicate an external bus access to an I/O
IOSTRB O/Z device. IOSTRB is placed in the high-impedance state in the hold mode; it also goes into the high-impedance
state when OFF is low.
Hold input. HOLD is asserted to request control of the address, data, and control lines. When acknowledged by
HOLD I
the 5416, these lines go into the high-impedance state.
† I = Input, O = Output, Z = High-impedance, S = Supply
‡ These pins have Schmitt trigger inputs.
§ This pin has an internal bus holder controlled by way of the BSCR register.
¶ This pin has an internal pullup resistor.
# This pin has an internal pulldown resistor.
Table 2–2. Signal Descriptions (Continued)
TERMINAL TERMINAL
I/O † I/O †
NAME NAME
MEMORY CONTROL SIGNALS (CONTINUED)
Hold acknowledge. HOLDA indicates to the external circuitry that the processor is in a hold state and that the
HOLDA O/Z address, data, and control lines are in the high-impedance state, allowing them to be available to the external
circuitry. HOLDA also goes into the high-impedance state when OFF is low.
Microstate complete. MSC indicates completion of all software wait states. When two or more software wait
states are enabled, the MSC pin goes active at the beginning of the first software wait state and goes inactive
MSC O/Z high at the beginning of the last software wait state. If connected to the READY input, MSC forces one external
wait state after the last internal wait state is completed. MSC also goes into the high-impedance state when OFF
is low.
Instruction acquisition signal. IAQ is asserted (active low) when there is an instruction address on the address
IAQ O/Z
bus and goes into the high-impedance state when OFF is low.
Clock output signal. CLKOUT can represent the machine-cycle rate of the CPU divided by 1, 2, 3, or 4 as
CLKOUT O/Z configured in the bank-switching control register (BSCR). Following reset, CLKOUT represents the
machine-cycle rate divided by 4.
Clock mode select signals. CLKMD1–CLKMD3 allow the selection and configuration of different clock modes
CLKMD1 ‡
such as crystal, external clock, and PLL mode. The external CLKMD1–CLKMD3 pins are sampled to determine
CLKMD2 ‡
I
the desired clock generation mode while RS is low. Following reset, the clock generation mode can be
CLKMD3 ‡
reconfigured by writing to the internal clock mode register in software.
Clock/oscillator input. If the internal oscillator is not being used, X2/CLKIN functions as the clock input. (This is
X2/CLKIN ‡
I
revision-dependent, see Section 3.10 for additional information.)
Output pin from the internal oscillator for the crystal. If the internal oscillator is not used, X1 should be left
X1 O unconnected. X1 does not go into the high-impedance state when OFF is low. (This is revision-dependent, see
Section 3.10 for additional information.)
Timer output. TOUT signals a pulse when the on-chip timer counts down past zero. The pulse is one CLKOUT
TOUT O/Z
cycle wide. TOUT also goes into the high-impedance state when OFF is low.
MULTICHANNEL BUFFERED SERIAL PORT 0 (McBSP #0), MULTICHANNEL BUFFERED SERIAL PORT 1 (McBSP #1),
AND MULTICHANNEL BUFFERED SERIAL PORT 2 (McBSP #2) SIGNALS
BCLKR0 ‡
Receive clock input. BCLKR can be configured as an input or an output; it is configured as an input following
BCLKR1 ‡
I/O/Z
reset. BCLKR serves as the serial shift clock for the buffered serial port receiver.
BCLKR2 ‡
BDR0
BDR1 I Serial data receive input
BDR2
BFSR0
Frame synchronization pulse for receive input. BFSR can be configured as an input or an output; it is configured
BFSR1 I/O/Z
as an input following reset. The BFSR pulse initiates the receive data process over BDR.
BFSR2
BCLKX0 ‡
Transmit clock. BCLKX serves as the serial shift clock for the McBSP transmitter. BCLKX can be configured as
BCLKX1 ‡
I/O/Z an input or an output, and is configured as an input following reset. BCLKX enters the high-impedance state when
BCLKX2 ‡
OFF goes low.
BDX0
Serial data transmit output. BDX is placed in the high-impedance state when not transmitting, when RS is
BDX1 O/Z
asserted, or when OFF is low.
BDX2
BFSX0 Frame synchronization pulse for transmit input/output. The BFSX pulse initiates the data transmit process over
BFSX1 I/O/Z BDX. BFSX can be configured as an input or an output, and is configured as an input following reset. BFSX goes
BFSX2 into the high-impedance state when OFF is low.
† I = Input, O = Output, Z = High-impedance, S = Supply
‡ These pins have Schmitt trigger inputs.
§ This pin has an internal bus holder controlled by way of the BSCR register.
¶ This pin has an internal pullup resistor.
# This pin has an internal pulldown resistor.
59
TERMINAL TERMINAL
DESCRIPTION DESCRIPTION
NAME NAME
HD0–HD7 ‡§
HCNTL0 ¶
HCNTL1 ¶
HBIL ¶
HCS ‡¶
HDS1 ‡¶
HDS2 ‡¶
HAS ‡¶
HR/W ¶
HRDY
HINT
HPIENA #
HPI16 #
CV SS
CV DD
DV SS
DV DD
† I = Input, O = Output, Z = High-impedance, S = Supply
‡ These pins have Schmitt trigger inputs.
§ This pin has an internal bus holder controlled by way of the BSCR register.
¶ This pin has an internal pullup resistor.
# This pin has an internal pulldown resistor.
TERMINAL TERMINAL
NAME NAME
TCK ‡¶
TDI ¶
DESCRIPTION DESCRIPTION
TDO
TMS ¶
TRST #
EMU0
TIMER SIGNALS
EMU1/OFF
† I = Input, O = Output, Z = High-impedance, S = Supply
‡ These pins have Schmitt trigger inputs.
§ This pin has an internal bus holder controlled by way of the BSCR register.
¶ This pin has an internal pullup resistor.
# This pin has an internal pulldown resistor.
Table 2–2. Signal Descriptions (Continued)
I/O † I/O †
DESCRIPTION DESCRIPTION
HOST-PORT INTERFACE SIGNALS
Parallel bidirectional data bus. The HPI data bus is used by a host device bus to exchange information with the
HPI registers. These pins can also be used as general-purpose I/O pins. HD0–HD7 is placed in the
high-impedance state when not outputting data or when OFF is low. The HPI data bus includes bus holders to
I/O/Z
reduce the static power dissipation caused by floating, unused pins. When the HPI data bus is not being driven
by the 5416, the bus holders keep the pins at the previous logic level. The HPI data bus holders are disabled
at reset and can be enabled/disabled via the HBH bit of the BSCR. These pins also have Schmitt trigger inputs.
Control inputs. HCNTL0 and HCNTL1 select a host access to one of the three HPI registers. The control inputs
I
have internal pullups that are only enabled when HPIENA = 0. These pins are not used when HPI16 = 1.
Byte identification. HBIL identifies the first or second byte of transfer. The HPIL input has an internal pullup
I
resistor that is only enabled when HPIENA = 0. This pin is not used when HPI16 = 1.
Chip select. HCS is the select input for the HPI and must be driven low during accesses. The chip select input
I
has an internal pullup resistor that is only enabled when HPIENA = 0.
Data strobe. HDS1 and HDS2 are driven by the host read and write strobes to control the transfer. The strobe
I
inputs have internal pullup resistors that are only enabled when HPIENA = 0.
Address strobe. Host with multiplexed address and data pins requires HAS to latch the address in the HPIA
I
register. HAS input has an internal pullup resistor that is only enabled when HPIENA = 0.
Read/write. HR/W controls the direction of the HPI transfer. HR/W has an internal pullup resistor that is only
I
enabled when HPIENA = 0.
Ready output. HRDY goes into the high-impedance state when OFF is low. The ready output informs the host
O/Z
when the HPI is ready for the next transfer.
Interrupt output. This output is used to interrupt the host. When the DSP is in reset, HINT is driven high
O/Z
goes into the high-impedance state when OFF is low. This pin is not used when HPI16 = 1.
HPI module select. HPIENA must be tied to DV DD to have HPI selected. If HPIENA is left open or connected to
ground, the HPI module is not selected, internal pullup for the HPI input pins are enabled, and the HPI data bus
I
has holders set. HPIENA is provided with an internal pulldown resistor that is always active. HPIENA is sampled
when RS goes high and is ignored until RS goes low again.
I HPI16 mode selection
SUPPLY PINS
S Ground. Dedicated ground for the core CPU
S +V DD . Dedicated power supply for the core CPU
S Ground. Dedicated ground for I/O pins
S +V DD . Dedicated power supply for I/O pins
Table 2–2. Signal Descriptions (Continued)
I/O † I/O †
DESCRIPTION DESCRIPTION
TEST PINS
IEEE standard 1149.1 test clock. TCK is normally a free-running clock signal with a 50% duty cycle. The changes
on test access port (TAP) of input signals TMS and TDI are clocked into the TAP controller, instruction register,
I
or selected test data register on the rising edge of TCK. Changes at the TAP output signal (TDO) occur on the
falling edge of TCK.
IEEE standard 1149.1 test data input. Pin with internal pullup device. TDI is clocked into the selected register
I
(instruction or data) on a rising edge of TCK.
IEEE standard 1149.1 test data output. The contents of the selected register (instruction or data) are shifted out
O/Z of TDO on the falling edge of TCK. TDO is in the high-impedance state except when the scanning of data is in
progress. TDO also goes into the high-impedance state when OFF is low.
IEEE standard 1149.1 test mode select. Pin with internal pullup device. This serial control input is clocked into
I
the TAP controller on the rising edge of TCK.
IEEE standard 1149.1 test reset. TRST, when high, gives the IEEE standard 1149.1 scan system control of the
I operations of the device. If TRST is not connected or driven low, the device operates in its functional mode, and
the IEEE standard 1149.1 signals are ignored. Pin with internal pulldown device.
Emulator 0 pin. When TRST is driven low, EMU0 must be high for activation of the OFF condition. When TRST
I/O/Z is driven high, EMU0 is used as an interrupt to or from the emulator system and is defined as input/output by way
of the IEEE standard 1149.1 scan system.
Emulator 1 pin/disable all outputs. When TRST is driven high, EMU1/OFF is used as an interrupt to or from the
emulator system and is defined as input/output by way of IEEE standard 1149.1 scan system. When TRST is
driven low, EMU1/OFF is configured as OFF. The EMU1/OFF signal, when active low, puts all output drivers into
the high-impedance state. Note that OFF is used exclusively for testing and emulation purposes (not for
I/O/Z
multiprocessing applications). Therefore, for the OFF condition, the following apply:
TRST = low,
EMU0 = high
EMU1/OFF = low
P, C, D, E Buses and Control Signals
54X cLEAD Single Access
TI BUS
XIO Enhanced XIO
16HPI
16 HPI
TMS320VC5416 Functional Block Diagram
60
. HINT
64K RAM
64K RAM
16K Program
Dual Access
ROM
Program Program/Data
MBus
GPIO
RHEA
RHEA Bus
Bridge
McBSP1
McBSP2
McBSP3
xDMA
RHEAbus TIMER
logic
APLL
JTAG
Clocks