Marantz ST7001/N1S Service Manual page 31

IC102 : AD1852JSR
16-/18-/20-/24-BIT
DIGITAL
DATA INPUT SERIAL
DATA
INTERFACE
2
SERIAL
MODE
Pin Input/Output
1 I
2 I
3 I
4 I
5 I
6
7 I
8 O
9 I
10 I
11, 15 I
12 O
13 O
14 O
16 O
17 O
18 I
19
20 I
21 I
22 O
23 I
24 I
25 I
26 I
27 I
28 I
Table I. Serial Data Input Mode
IDPM1 (Pin 20) IDPM0 (Pin 21)
0 0
0 1
1 0
1 1
VOLUME
MUTE
AD1852
8 F
ATTEN/
S
INTERPOLATOR
MUTE
ATTEN/ 8 F
S
MUTE
INTERPOLATION
MUTE
Pin Name Description
DGND Digital Ground.
MCLK Master Clock Input. Connect to an external clock source at either 256 F
512 F , 768 F
S
CLATCH Latch Input for Control Data. This input is rising-edge sensitive.
CCLK Control Clock Input for Control Data. Control input data must be valid on the rising
edge of CCLK. CCLK may be continuous or gated.
CDATA Serial Control Input, MSB first, containing 16 bits of unsigned data per channel. Used
for specifying channel-specific attenuation and mute.
NC No Connect.
192/ Selects 48 kHz (LO) or 192 kHz Sample Frequency.
ZEROR Right Channel Zero Flag Output. This pin goes HI when Right Channel has no signal
input for more than 1024 LR Clock Cycles.
DEEMP De-Emphasis. Digital de-emphasis is enabled when this input signal is HI. This is used
to impose a 50 μs/15 μs response characteristic on the output audio spectrum at an
assumed 44.1 kHz sample rate. Curves for 32 kHz and 48 kHz sample rates may be
selected via SPI control register.
96/ Selects 48 kHz (LO) or 96 kHz Sample Frequency.
AGND Analog Ground.
OUTR+ Right Channel Positive Line Level Analog Output.
OUTR– Right Channel Negative Line Level Analog Output.
FILTR Voltage Reference Filter Capacitor Connection. Bypass and decouple the voltage refer-
ence with parallel 10 μF and 0.1 μF capacitors to the AGND.
OUTL– Left Channel Negative Line Level Analog Output.
OUTL+ Left Channel Positive Line Level Analog Output.
AVDD Analog Power Supply. Connect to Analog 5 V Supply.
Filter Capacitor Connection. Connect 10 μF capacitor to AGND (Pin 15).
FILTB
IDPM1 Input Serial Data Port Mode Control One. With IDPM0, defines 1 of 4 serial modes.
IDPM0 Input Serial Data Port Mode Control Zero. With IDPM1, defines 1 of 4 serial modes.
ZEROL Left Channel Zero Flag Output. This pin goes HI when Left Channel has no signal
input for more than 1024 LR Clock Cycles.
MUTE Mute. Assert HI to mute both stereo analog outputs. Deassert LO for normal operation.
Reset. The AD1852 is reset on the rising edge of this signal. The serial control port
registers are reset to the default values. Connect HI for normal operation.
L/ CLK Left/ Clock Input for Input Data. Must run continuously.
BCLK Bit Clock Input for Input Data. Need not run continuously; may be gated or used in a
burst fashion.
SDATA Serial Input, MSB first, containing two channels of 16, 18, 20, and 24 bits of twos
complement data per channel.
DVDD Digital Power Supply Connect to digital 5 V supply.
Serial Data Input Format
Right-Justified
2
I S-Compatible
Left-Justified
DSP
CONTROL DATA
INPUT
3
SERIAL CONTROL VOLTAGE
INTERFACE REFERENCE
MULTIBIT SIGMA-
DAC
DELTA MODULATOR
MULTIBIT SIGMA-
DAC
DELTA MODULATOR
2
DE-EMPHASIS ANALOG
SUPPLY
, or 1024 F .
S S
37
DIGITAL CLOCK
SUPPLY IN
2
AUTO-CLOCK
DIVIDE CIRCUIT
ANALOG
OUTPUTS
2
ZERO
FLAG
, 384 F
S
,
S