Onkyo TX-SR804 Service Manual page 120

IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS -26
Q8001 : SII504 (I/P Video Converter)
BLOCK DIAGRAM
Serial or
parallel bus
Interlaced
Video Input
Serial Audio Input
Serial Audio Output
Video Output Section BLOCK DIAGRAM
Bypass
Frame Data
Horizontal
From
Scaler
SDRAM
Controller
Host
Interface
Configuration Register Outputs
Video Deinterlace
Input
Audio/
Video
Field
Sync
Data
Audio
Data
Memory Controller
SDRAM
Control, Address,
and Data
Bypass Bypass
4:2:2
to Dither
4:4:4 Generator
Conversion
Video
Start Frame Transfer
Timing
Generator
GenLock
From
Video Input
C
L
Clock
O
C
Generation
K
S
Video
Processor Output
Field Frame Frame
Data Data Data
Bypass
YC C
r b
to
RGB
Conversion
Pixel
Clock
TX-SR804/804E
27 MHz
Master Clock
Progressive
Video Output
Bypass
10-bit
RGB/
Color
YCrCb
Lookup
Output
Table
Syncs,
Blank,
LCD Pwr