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IC51 : T5CD2
Pin
Port Name
No.
51 P07/AD7
52 P10/AD8/A8
53 P11/AD9/A9
54 P12/AD10/A10
55 P13/AD11/A11
56 P14/AD12/A12
57 P15/AD13/A13
58 P16/AD14/A14
59 P17/AD15/A15
60 P20/A0/A16
61 P21/A1/A17
62 DVSS
63 /NMI
64 DVCC
65 P22/A2/A18
66 P23/A3/A19
67 P24/A4/A20
68 P25/A5/A21
69 P26/A6/A22
70 P27/A7/A23
71 PZ0/RD
72 PZ1/WR
73 PZ2/HWR
74 PZ3/R/W
75 P30/TB3IN0/INT3/SDA0 I/O
76 P31/TB3IN1/INT4/SCL0 I/O
77 P32/WAIT/TB3OUT0
78 P33/TB3OUT1
79 PB0/TB4IN0/INT9/SDA1 I/O
80 PB1/TB4IN1/INT10/
SCL1
81 PB2/TB4OUT0
82 PB3/TB4OUT1
83 DVCC
84 DVSS
85 P50/AN0
86 P51/AN1
87 P52/AN2
88 P53/AN3
89 P54/AN4
90 P55/AN5
91 P56/AN6
92 P57/AN7
93 P60/AN8
94 P61/AN9
95 P62/AN10
96 P63/AN11
97 P64/AN12
98 P65/AN13
99 P66/AN14
100 P67/AN15
Power
I/O Use
Name
off
I/O
O
L
SRAM_ADD07
I/O
I
I
CD_BUS2
I/O
O
L
CD_BUS3
I/O
O
L
CD_BUCK
I/O
O
L
CD_CCE
I/O
O
L
DSP_RESET
I/O
O
L
MT_STBY
I/O
O
L
CD_CLOSE_M
I/O
O
L
CD_OPEN_M
I/O
NC
I/O
I
I
CD_OPEN_SW
DVSS
/NMI
DVCC
I/O
I
I
CD_CLOSE_SW
I/O
NC
I/O
I
I
CD_LIMIT_SW
I/O
O
L
VFD_POWER
I/O
O
H
F_MUTE
I/O
O
L
DISPLAY_P
I/O
O
L
DAC_RESET
I/O
O
L
NC
I/O
O
L
DAC_CLK
I/O
O
L
DAC_DATA
O
L
TRANS_ON/OFF
O
L
MP3_LED_P
I/O
O
L
WMA_LED_P
I/O
NC
O
L
PLL_SDA_
I/O
O
L
PLL_SCL
I/O
O
L
PLL_PLL
I/O
O
L
PLL_EX_SEL
DVCC
DVSS
I/O
I
I
KEY0
I/O
I
I
KEY1
I/O
I
I
KEY2
I/O
NC
I/O
NC
I/O
NC
I/O
NC
I/O
NC
I/O
O
L
SRAM_ADD08
I/O
O
L
SRAM_ADD09
I/O
O
L
SRAM_ADD10
I/O
O
L
SRAM_ADD11
I/O
O
L
SRAM_ADD12
I/O
O
L
SRAM_ADD13
I/O
O
L
SRAM_ADD14
I/O
NC
Port Setting
Act.
init
-
I
sram_address_07
-
I
receive data from CD DSP
-
I
send command to CD DSP
-
I
communication clock with CD DSP
L
I
communication chip enable with CD DSP
L
I
CD DSP reset
H
I
motor stanby
H
I
cd close motor
H
I
cd open motor
open
-
I
cd open switch
GND
external interrupt, connect with +5V
MCU power, connect with +5V
-
I
cd close switch
open
-
I
cd inner switch
H
I
vfd blink control
H
I
preout mute control
L
I
FIP display on/off control
L
H
DAC reset
open
-
I
DAC clock
-
I
DAC data
H
I
trans change control
H
I
MP3 LED control
H
I
WMA LED control
open
-
I
Pitch data Control
-
I
Pitch clock Control
L
I
Pitch chip enable Control
-
I
PLL Ex Select Pin
MCU power, connect with +5V
GND
-
I
key1 input
-
I
key2 input
-
I
key3 input
open
open
open
open
open
-
I
sram_address_08
-
I
sram_address_09
-
I
sram_address_10
-
I
sram_address_11
-
I
sram_address_12
-
I
sram_address_13
-
I
sram_address_14
open
43
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