IBM System 360 Operating Manual page 22

Switch A Setting
MPX
0
MPX 1
MPX2
MPX3
MPX4
MPX5
MPX
6
LS
Auxiliary Storage Accessed
Multiplexor Channel Unit Con-
trol Words 0 through 31
Multiplexor Channel Unit
Control Words 32 through 63
Multiplexor Channel Unit
Control Words 64 through 95
Multiplexor Channel Unit
Control \Vords 96 through 127
Multiplexor Channel Unit
Control Words 128 through
159
Multiplexor Channel Unit Con-
trol ':Vords 160 through 191
Multiplexor Channel Unit Con-
trol Words 192 through 223
Local Storage
Note: The MPX 0 setting is on all 2030 consoles.
The lVIPX
1
and MPX 2 settings are on all 2030} s
that have 16K or more main-storage addresses.
MPX 3, MPX 4, MPX
5,
and MPX 6 settings are
on 2030'
s
(with 32K or more main-storage addresses)
that have the 224 subchannel special feature.
2. Set rotary switch B to
O.
3. Set the desired byte address in rotary switches
C and D as described in the following sections.
General-Purpose Register Selection
C'JBneral-purpose registers 0 through 15 are selected
by setting switch C to the eorres ponding hexadecimal
equivalent (0 for register 0, F for register 15).
The desired byte in the selected general regis-
ter is specified by switch
D
(bytes 0 through 3 by
switch poSitions 0 through 3).
Floating-Point Register (Special Feature)
Selection
Floating-point registers 0, 2, 4, and 6 are se-
lected by setting switch C to 0, 2, 4, or 6, res pec-
tively.
22
The desired byte in the selected floating-point
register is specified by switch D
as
follows:
Switch D Setting Selected Byte
8 0
9
1
A 2
B 3
C 4
D 5
E 6
F 7
In all floating-point formats, the sign is con-
tained in the high-order bit (bit 0) of byte 0 and the
characteristic is contained in bit positions
1
through
7 of byte O.
In short floating-point formats, the fraction is
contained in bytes 1, 2, and
3.
In long floating-
point formats, the fraction is contained by bytes
1,2,3,4,5, 6, and 7.
CPU-Registers Stored in Local Storage
During multiplexor-channel operations CPU registers
are temporarily stored in loeal storage. To display
or store in this area:
1. Set switch
C
to 5.
2. Set switch D to the desired register storage as
follows:
Stored Register Selected (Cnmeral
Switch D Setting Function)
8
9
A
B
C
D
E
F
~
}
G
U
1
vf
L
D
S
(Instruction Address)
(Instruction Operation Code)
(Data Address)
(Instruction Length)
(General-Purpose Data
Register)
(CPU Status)
Unit Control Word (UCW) Selection
1. Make sure that switch A is set to the proper IVIPX
setting (MPX 0 to MPX 6, depending upon model
and features).