Sony SCD-XA9000ES Service Manual page 84

SCD-XA9000ES
Pin No. Pin Name
VDD
61
VSS
62
63 DLDRI
CSWI
64
SLSRI
65
FLFRI
66
67 TEST3
CLK512
68
VSS
69
XRST
70
VDD
71
SCLK
72
XCS
73
SI
74
SO
75
DEXRI
76
DMLI
77
DMRI
78
VSS
79
80 PHAI
81 BCKAI
82 DQM
DLI
83
84 DRI
DCI
85
DLFEI
86
DLSI
87
88 DRSI
VSS
89
90 to 95 D15 to D10
VDD
96
97, 98 D9, D8
GND
99
100 D0
84
I/O
—
Power supply terminal (+3.3V)
—
Ground terminal
I Analog audio data input terminal Not used
I
Center and sub woofer audio data input terminal Not used
I
Surround audio data input terminal Not used
I
Front audio data input terminal Not used
I Input terminal for the test
I
Master clock signal (22.5792 MHz) input terminal
—
Ground terminal
I
Reset signal input from the CPU "L": reset
—
Power supply terminal (+3.3V)
I
Serial clock signal input from the CPU
I
Chip select signal input from the CPU
I
Serial data input from the CPU
O
Serial data output to the CPU
I
Not used
I
DSD data input terminal for L-ch down mix Not used
I
DSD data input terminal for R-ch down mix Not used
—
Ground terminal
I Clock signal (2.8224 MHz) input terminal
I
Clock signal (5.6448 MHz) input terminal
O
Not used
I
Front L-ch DSD data input from DSD decoder
O Front R-ch DSD data input from DSD decoder
O
Center DSD data input from DSD decoder
O
Sub woofer DSD data input from DSD decoder
O
Surround L-ch DSD data input from DSD decoder
O Surround R-ch DSD data input from DSD decoder
—
Ground terminal
I/O
Two-way data bus with the SD-RAM
—
Power supply terminal (+3.3V)
I/O Two-way data bus with the SD-RAM
—
Ground terminal
I/O
Two-way data bus with the SD-RAM
Description