Sony SCD-XA9000ES Service Manual page 78

SCD-XA9000ES
Pin No. Pin Name
120 VCOR1
121 VCOIN
122, 123 GNDA4, GNDA3
124 LPF5
125 VC1
126, 127 LPF2, LPF1
128, 129 VCCA3, VCCA2
130 PDO
131 PDHVCC
132 FDO
133, 134 GNDA2, GNDA1
135 SPO
136 VC2
137 MDIN2
138 MDIN1
139 VCCA1
140 CLVS
141 VSS
142 MDSOUT
143 VDD
144 MDPOUT
145 DEFECT
146 GSCOR
147 EXCK
148 SBIN
149 VSS
150 SCOR
151 WFCK
152 VDD5V
153 XRCI
154 VDDS
155 C2PO
156 VDD
157 DBCK
158 BCLK
159 DDAT
160 MDAT
161 VSS
162 DLRC
163 LRCK
164 XRST
165 IFS0
166 IFS1
167 XTAL
168 VSS
169 XTA2
170 XTA1
78
I/O
—
VCO oscillating range setting resistor connected terminal
I
VCO input terminal
— Ground terminal (analog system)
O
Signal output from the operation amplifier from PLL loop filter
I
Middle point voltage (+1.65V) input terminal
I
Inverted signal input to the operation amplifier from PLL loop filter
— Power supply terminal (+3.3V) (analog system)
O
Signal output from the charge pump for phase comparator
I
Middle point voltage input terminal for RF PLL
O
Signal output from the charge pump for frequency comparator
—
Ground terminal (analog system)
O
Spindle motor control signal output terminal
I
Middle point voltage (+1.65V) input terminal
I
Spindle motor servo drive signal input terminal
I
MDP input terminal
—
Power supply terminal (+3.3V) (analog system)
O
Control signal output for selection the spindle control filter constant at CLVS
—
Ground terminal (digital system)
O
Frequency error output terminal of internal CLV circuit
—
Power supply terminal (+3.3V) (digital system)
O
Phase error output terminal of internal CLV circuit
I
Defect signal input from the digital signal processor
I
Guard subcode sync (S0+S1) detection signal input from the digital signal processor
O
Subcode serial data reading clock signal output to the digital signal processor
I
Subcode serial data input from the digital signal processor
—
Ground terminal (digital system)
I
Subcode sync (S0+S1) detection signal input from the digital signal processor
I Write frame clock signal input from the digital signal processor
—
Power supply terminal (+5V)
I
RAM overflow signal input terminal Not used
—
Power supply terminal (+5V) (digital system)
I C2 pointer signal input from the digital signal processor
—
Power supply terminal (+3.3V) (digital system)
O
Bit clock signal (2.8224 MHz) output terminal Not used
I
Bit clock signal (2.8224 MHz) input from the digital signal processor
O PCM data output terminal Not used
I
Serial data input from the digital signal processor
—
Ground terminal (digital system)
O
L/R sampling clock signal (44.1 kHz) output terminal Not used
I L/R sampling clock signal (44.1 kHz) input from the digital signal processor
I
Reset signal input from the I/O expander "L": reset
I
Interface selection signal input terminal Fixed at "L" in this set
I
Interface selection signal input terminal Fixed at "H" in this set
I 33.8688 MHz clock signal input terminal
—
Ground terminal (digital system)
O
System clock output terminal (33.8688 MHz)
I
System clock input terminal (33.8688 MHz)
Description