Tmp93Cs40F (Au: Ic301); Tmp93Cs40F Terminal Function - Denon AVR-2802 Service Manual
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Also See for AVR-2802:
- Operating instructions manual (255 pages) ,
- Service manual (74 pages) ,
- Brochure & specs (2 pages)
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TMP93CS40F (AU: IC301)
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TMP93CS40F Terminal Function
Pin
Name
Symbol
I/O Type
Op
Det
No.
1
V REFL
←
2
A Vss
←
3
A Vcc
4
_NMI
I
5
P70/TI0
C15
O
C
Ed
6
P71/TO1
C16
O
C
Ed
7
P72/TO2
C17
O
C
Ed
8
P73/TO3
ROM/RAM
O
C
Ed
9
P80/INT4/TI4
_INTREQ OUT
I/O
C
Eu
E↓&L
10
P81/INT5/TI5
B.DOWN
I
Eu
E↑&L
11
P82/TO4
O
C
12
P83/TO5
_REQ
O
C
Eu
13
P84/INT6/TI6
_ACK
I
Eu
E↓&L
14
P85/INT7/TI7
ERR
I
E↑&L
15
P86/TO6
I
Lv
16
P97/INT0
_CS
I
Ed
E↑&L
17
P90/TXD0
SI
O
C
18
P91/RXD0
SO
I
19
P92/_CTS0/SCLK0 CLK
I/O
C
20
P93/TXD1
O
C
21
P94/RXD1
O
C
22
P95/SCLK1
O
C
←
23
AM8/_16
24
CLK
O
C
Eu
←
25
Vcc
26
Vss
I/O1
27
X1
Xin
I
28
X2
Xout
O
←
29
_EA
30
_RESET
RESET2_
I
Eu
Lv
31
P96/XT1
A/D RESET
O
N
Eu
32
P97/XT2
O
C
Ed
←
33
TEST1
I
←
34
TEST2
I
35
PA0
DINA
O
C
Ed
36
PA1
DINB
O
C
Ed
37
PA2
O
C
38
PA3
DINC
O
C
Ed
39
PA4
DOUTA
O
C
Ed
40
PA5
DOUTB
O
C
Ed
#
#
$
#
Res
Init
Function
A/D ref. GND
A/D GND
AD +5V
Not used (fixed to H)
L
L
Fixed to L (DSP ROM address cont. out bit 15, not used)
L
L
DSP program ROM address cont. out bit 16
L
L
DSP program ROM address cont. out bit 17
L
L
ROM/RAM switching control terminal (L:ROM)
Z
DSP request input and cont. output (L:Rq & cont.)
Z
Power down detect (H: Detected)
L
L
MAIN-SUB CPU comm. control output (L: Comm. request from
H
L
sub)
MAIN-SUB CPU comm. control input (L: Ack. return from main)
DIR control input terminal (LC89055Q)( H: ERR)
Z
(GND)
DIR control input terminal (LC89055Q), when CH status change
L→H
MAIN-SUB CPU comm. control terminal (data output)
MAIN-SUB CPU comm. control terminal (data input)
MAIN-SUB CPU comm. control terminal (I2C clock in/output)
Z
L
Z
L
Z
L
Fixed to +5V
+5V
GND
X'tal connection
X'tal connection
Fixed to +5V
L
Reset input (controlled by main CPU)
H
H
A/D control terminal (L: Reset)
L
L
Connected to TEST2
Connected to TEST1
L
L
Digital input switching control output
L
L
Digital input switching control output
L
L
L
L
Digital input switching control output
L
L
Digital output switching control output
L
L
Digital output switching control output
Pin
Name
Symbol
I/O Type
Op
Det
No.
41
PA6
DEEMP
O
C
Ed
42
PA7/SCOUT
96k-DAC
O
C
43
ALE
O
C
44
Vcc
45
P00/AD0
(AD0)
I/O
C
46
P01/AD1
(AD1))
I/O
C
47
P02/AD2
(AD2)
I/O
C
48
P03/AD3
(AD3)
I/O
C
49
P04/AD4
(AD4)
I/O
C
50
P05/AD5
(AD5)
I/O
C
51
P06/AD6
(AD6)
I/O
C
52
P07/AD7
(AD7)
I/O
C
53
P10/AD8/A8
(A8)
O
C
54
P11/AD9/A9
(A9)
O
C
55
P12/AD10/A10
(A10)
O
C
56
P13/AD11/A11
(A11)
O
C
57
P14/AD12/A12
(A12)
O
C
58
P15/AD13/A13
(A13)
O
C
59
P16/AD14/A14
(A14)
O
C
60
P17/AD15/A15
(A15)
O
C
←
61
_WDTOUT
O
C
←
62
Vss
←
63
Vcc
64
P20/A0/A16
(A16)
O
C
65
P21/A1/A17
DIR CLK
O
C
66
P22/A2/A18
DIR CE
O
C
67
P23/A3/A19
DIR MOSI
O
C
68
P24/A4/A20
DIR MOSO
I
Lv
69
P25/A5/A21
FGAIN
O
C
Ed
70
P26/A6/A22
DAC-RESET
O
C
Ed
71
P27/A7/A23
SEL CK
O
C
72
P30/_RD
(_RD)
O
C
73
P31/_WR
(_WR)
O
C
74
P32/_HWR
CSI
I
Lv
75
P33/_WAIT
ERR MUTE_
O
C
Ed
76
P34/_BUSRQ
I
Lv
77
P35/_BUSRQ
DIG.(AC3) MUTE
O
C
Ed
78
P36/_R/W
I
Lv
79
P37/_RAS
DIR RESET
O
C
80
P40/_CS0/_CAS0
O
C
81
P41/_CS1/_CAS1
O
C
82
P42/_CS2/_CAS2 (_CS0)
O
C
83
P60/PG00
DSP. RESET
O
C
84
P61/PG01
I/02 SCD OUT
I
C
Lv
85
P62/PG02
I/03 DSP. CS
O
86
P63/PG03
I/04 DSP. CLK
O
C
87
P64/PG10
I/05 SCD IN
O
C
88
P65/PG11
I/06 4527_CE
O
C
89
P66/PG12
I/07 4527_CLK
O
C
90
P67/PG13
I/08 4527_DIN
O
C
←
91
Vss
92
P50/AN0
INTTREQ IN
I
Eu
Lv
93
P51/AN1
I
Eu
Lv
94
P52/AN2
EMP
I
Lv
95
P53/AN3
96K DET
I
Lv
96
P54/AN4
I
Eu
Lv
97
P55/AN5
I
Eu
Lv
98
P56/AN6
ACC ON/OFF
I
Eu
Lv
99
P57/AN7
I
Eu
Lv
←
100 V REFH
AVR-2802/982
Res
Init
Function
L
L
DAC de-emphasis filter cont. out terminal (H:ON)
L
L
DAC control terminal (H: Sample frequency 96kHz)
L
L
(Address latch enable)
+5V
Z
L
(EPROM data in D0 / address out A0)
Z
L
(EPROM data in D1 / address out A1)
Z
L
(EPROM data in D2 / address out A2)
Z
L
(EPROM data in D3 / address out A3)
Z
L
(EPROM data in D4 / address out A4)
Z
L
(EPROM data in D5 / address out A5)
Z
L
(EPROM data in D6 / address out A6)
Z
L
(EPROM data in D7 / address out A7)
Z
L
(EPROM address out A8)
Z
L
(EPROM address out A9)
Z
L
(EPROM address out A10)
Z
L
(EPROM address out A11)
Z
L
(EPROM address out A12)
Z
L
(EPROM address out A13)
Z
L
(EPROM address out A14)
Z
L
(EPROM address out A15)
Z
H
Watch dog output
GND
+5V
Z
L
(EPROM address out A16)
Z
L
DIR control terminal (LC89055Q) control clock output
Z
L
DIR control terminal (LC89055Q) control chip enable output
Z
L
DIR control terminal (LC89055Q) control data output
DIR control terminal (LC89055Q) control data input
L
L
FRONT ch GAIN switching control output (H: SW=NO)
DAC control terminal (L: Power down mode, ↑(rising edge) Reset)
L
H
Z
L
ADC/DIR data clock switching control terminal (L: ADC)
Z
L
(Flash memory control terminal)
Z
L
(Flash memory control terminal)
DIR control input terminal (L: PCM)
L
L
Pop noise preventive mute control output (L: Mute)
Z
GND
Z
L
Digital mute control output (L: AC-3 or DTS decode enable)
Z
GND
Z
L
DIR control output (LC89055Q) (L: Reset)
Z
L
Z
L
Z
L
(Flash memory control terminal)
Z
L
DSP reset output terminal (L:Reset)
Z
DSP status data input terminal
Z
L
DSP chip select cont.output (L:Data out)
Z
L
DSP data clock output terminal
Z
L
DSP data output terminal
Z
L
AD control terminal (AK4527), Chip enable output
Z
L
AD control terminal (AK4527), Data clock output
Z
L
AD control terminal (AK4527), Data output
GND
Z
Z
H: EMP on
96k signal detect input, H: 96k
Z
Z
Z
Z
AD ref. +5V
16
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