Model 1597 2~1 - Keithley 181 Service Manual

I
THEORY OF OPERATION
MODEL 181
Input Disable
FIGURE 4-5 Charge Balance Single Slope Phase
4-14 Display
The display lr,formation is outputted on PA0 through PA7 on
the VIA II/O1 bus. The information is updated at a 1.2kHr rate
which means each digit is on for 833 microseconds. Each up-
date begins by presenting new segment information on the
VIA II/O1 bus (PA0 PA71 and outputting a clock pulse oil
CAZ. The clock pulse goes to U203, which is a shift register on
the display board. U203 shifts a digit enable bit 10 the next
digit to be enabled. Ever" eiqht times the displav is updated. a
digitenable bit isgeneratedat P85andgoesto theenabledata
input of the shift register,
V201 C. V2028 and V202C drive the rows of the switch matrix.
~The switches are arranged in a 4 by 4 matrix, eleven of which
are used. The columns of the switch matrix go to Bits O-3 of
the switch ports
The switch port IS located on the motherboard fn Schematic
30583D. Sheet 2 01 2, Sectlo" F5. The segment dwers are
0201 0208~ 111 additlor to driwng the various segments, they
also artivak Ihe appropriale LCD's,
4-15. DIA Converter
The heart of the D/A section is U117, shown on Schematic
30583D. Sheet 1 of 2~ It is a standard 12~bit D/A converter.
Data for the D/A IS multiplexed with the display data and is
latched info U116. This data is converted into an output cur-
rent. Ul18 IS configured as a current-to~voltage converter.
Capacitor Cl10 compensates for output capacitance of Ull7.
The output voltage from U118 swings from OV to -1OV. since
ouiput current flows through RF which is internai to Ulll
lAD75411. All bits off yields OV output at Ull8; all bits ON
yields ~IOV output at Ul18.
0 TO countet
VR102 is configured as a rcfcrence for Ihe D/A circuil. RIO/,
R108, RI09 arrd U119B scale the reference to ! 1OV. R107
provides an adjustment range on the + 1OV reference which
calibrates positive Full Scale An offset for U119A is provided
by Rlll, R112, R106 and VR102. This offset plus R113 and
R114 provide the scaling which translates the OV to 1OV
swing loutput of U1181 to Ihe desired 2 to +~ 2V swing. R106
calibrates negative full scale by altering the offset voltage on
UllSA,
Capacitor Cl37 filters the output and prevents it from appear
ing like a staircase waveform. VRlO3, VRIO4 and RI30 arc
configured as protection in case the analog output terminals
should be momentarily shorted together or tied to groater lhan
+3ov.
4-16. Nanovolt Presmp
During the theory of operation of the Nanovolt preamp, it will
be helpful to refer to the Schematic Diagram 30856D
4.17. Low Noise Design
One of the major reasons for utilizing a differential input stage
is the Supply Noise Reiec~ion Without proper matching,
power supply noise would have to be or a submicrovolt level
which would be impossible at low frequencies, Both bias cur
rent nom and voltage noise arc the major components of
Supply Noise. In order to minimize voltage noise, a pair of low
noise bipolar supplies are generated on the Nanovolt Preamp
board using U405 and IIS associated componen& VR403 and
VR404 serve as references (6.2 volts1 and R421, R422 and R413
scale the outpur voltages / ~+VRI 10 the desired f lOvolt Ievcl~
By providing the attenuation above 0.3Hr. C412 and C413 pre
vent ampllficafion of U405's input voltage news U404A
bootstraps these supplies to improve amplifier linearity. The
noise conirlbution from reference zeners VR403 and VA404 IS
4-4