Model 1488 2~1 - Keithley 181 Service Manual

I
THEORY OF OPERATION MODEL 181
TABLE 4-l
MICROCOMPUTER MEMORY MAP
X5B30, Sheet 2 of 2 and 305&D, The digital cont~9 civails
of the 181 AID are located on Schematic 30583D. Sheet 2 of 2
while the circuits that they control are located on Schematic
30585D.
The conversion from analog data 10 digital data begins with
the integration cycle. Refer to Figures 4~3 and 4~4. An inte-
gration cycle begins with the appropriate signals to the input
amplifier and preamplifier enabled by one 01 more of the Sl
thru S12 lines going to a logic "1". The charge balance line will
go to a logic "1" after the microprocessor waits for the input
to settle. The "D" Input of U122A also goes to a logic "1" and
is gated 10 U123B through U127B. This clears the 16 bit
counter U123B. The Q output of U122A will enable the input
signal to the integrator on the next rising edge of the 2.5kHr
clock. The microprocessor waits 16.66 milliseconds (the in&
gralion period lor 60Hr. 20~00 miillseconds for 60HrI then the
charge balance start line goes 10 logic "0". At the next rising
edge of the clock, the Q output goes to a logic "1" again. This
WIII disable thn Input to the integrator and ends the exact 16,66
millisecond integration period.
Charge Balance Flip-Flop
FIGURE 4.2. AID Control Logic
While the integration pcrlod is taking place, pulses from the
V~F arc inputted into the l&bit counter U123B. When the
co""tcr overflows after 16 cowts, clock pulses are genoiared
which the VIA counts in an internal counter. These clock
pulses become the most significant bits of the result.
24-Bit Result
8 Bits These bits are generated by clock puises
during the Charge Balance phase.
4 Bits This is llhe remainder left on Ihn l&bit
cou"lcr durinij ,he CB phase.
8 Bits These counts are accumulated in the
16 bii counter during the single slope phase.
4 Bits This is Ihe remainder left on the 16~bir
counter during the sin(~lc slope phase,
4-2