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Figure 24 shows CT voltage and also by Channel 2 the
switch's drain voltage at light load conditions.
Figure 24. CT and Drain at Light Load
The waveform on the current sense pin at full load
conditions can be observed from Channel 3 in Figure 25.
Figure 25. CS Pin at Full Load Condition
NCP1215
Figure 26 demonstrates the reduction of the peak primary
current at light load conditions.
Figure 26. CS Pin at Light Load Condition
Gate−Source Resistor Design Guidelines
In some applications, there is a need to wire a resistor
between the MOSFET gate and source connections. This
can preclude an eventual MOSFET destruction if, in the
production stage, the converter is powered whilst the gate is
left unconnected. However, dealing with an extremely low
startup current implies a careful selection of the gate−source
resistance. With the NCP1215, the gate−source resistor must
be calculated to allow the growth of the V
4.0 V in order to not interfere with the power−on sequence.
The following equation helps deriving Rgate−source,
accounting for the minimum rectified input voltage and the
startup resistor: Vin
Rstartup) u 4.0 V. If we take a Vin
resistor of 4.0 MW, then Rgate−source equals 180 kW as a
minimum normalized value.
http://onsemi.com
13
capacitor to
CC
x Rgate−source/(Rgate−source +
min
of 100 VDC, a startup
min
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