Philips HDD100 Service Manual page 9

PIN DESCRIPTIONS OF IC CY7C68013
Table 4-1. FX2 Pin Descriptions
128 100 56 56
TQFP TQFP SSOP QFN
77 62
78 63
79 64
PORT D
102 80 52 45 PD0 or
103 81 53 46 PD1 or
104 82 54 47 PD2 or
105 83 55 48 PD3 or
121 95 56 49 PD4 or
122 96 1 50 PD5 or
123 97 2 51 PD6 or
124 98 3 52 PD7 or
Port E
108 86
109 87
110 88
[5]
(continued)
Name Type Default
PC5 or I/O/Z
GPIFADR5 (PC5)
PC6 or I/O/Z
GPIFADR6 (PC6)
PC7 or I/O/Z
GPIFADR7 (PC7)
I/O/Z
FD[8] (PD0)
I/O/Z
FD[9] (PD1)
I/O/Z
FD[10] (PD2)
I/O/Z
FD[11] (PD3)
I/O/Z
FD[12] (PD4)
I/O/Z
FD[13] (PD5)
I/O/Z
FD[14] (PD6)
I/O/Z
FD[15] (PD7)
PE0 or I/O/Z
T0OUT (PE0)
PE1 or I/O/Z
T1OUT (PE1)
PE2 or I/O/Z
T2OUT (PE2)
3 - 4
I Multiplexed pin whose function is selected by PORTCCFG.5
PC5 is a bidirectional I/O port pin.
GPIFADR5 is a GPIF address output pin.
I Multiplexed pin whose function is selected by PORTCCFG.6
PC6 is a bidirectional I/O port pin.
GPIFADR6 is a GPIF address output pin.
I Multiplexed pin whose function is selected by PORTCCFG.7
PC7 is a bidirectional I/O port pin.
GPIFADR7 is a GPIF address output pin.
I Multiplexed pin whose function is selected by the IFCONFIG[1..0]
and EPxFIFCFG.0 (wordwide) bits.
FD[8] is the bidirectional FIFO/GPIF data bus.
I Multiplexed pin whose function is selected by the IFCONFIG[1..0]
and EPxFIFCFG.0 (wordwide) bits.
FD[9] is the bidirectional FIFO/GPIF data bus.
I Multiplexed pin whose function is selected by the IFCONFIG[1..0]
and EPxFIFCFG.0 (wordwide) bits.
FD[10] is the bidirectional FIFO/GPIF data bus.
I Multiplexed pin whose function is selected by the IFCONFIG[1..0]
and EPxFIFCFG.0 (wordwide) bits.
FD[11] is the bidirectional FIFO/GPIF data bus.
I Multiplexed pin whose function is selected by the IFCONFIG[1..0]
and EPxFIFCFG.0 (wordwide) bits.
FD[12] is the bidirectional FIFO/GPIF data bus.
I Multiplexed pin whose function is selected by the IFCONFIG[1..0]
and EPxFIFCFG.0 (wordwide) bits.
FD[13] is the bidirectional FIFO/GPIF data bus.
I Multiplexed pin whose function is selected by the IFCONFIG[1..0]
and EPxFIFCFG.0 (wordwide) bits.
FD[14] is the bidirectional FIFO/GPIF data bus.
I Multiplexed pin whose function is selected by the IFCONFIG[1..0]
and EPxFIFCFG.0 (wordwide) bits.
FD[15] is the bidirectional FIFO/GPIF data bus.
I Multiplexed pin whose function is selected by the PORTECFG.0 bit.
PE0 is a bidirectional I/O port pin.
T0OUT is an active-HIGH signal from 8051 Timer-counter0.
T0OUT outputs a high level for one CLKOUT clock cycle when
Timer0 overflows. If Timer0 is operated in Mode 3 (two separate
timer/counters), T0OUT is active when the low byte timer/counter
overflows.
I Multiplexed pin whose function is selected by the PORTECFG.1 bit.
PE1 is a bidirectional I/O port pin.
T1OUT is an active-HIGH signal from 8051 Timer-counter1.
T1OUT outputs a high level for one CLKOUT clock cycle when
Timer1 overflows. If Timer1 is operated in Mode 3 (two separate
timer/counters), T1OUT is active when the low byte timer/counter
overflows.
I Multiplexed pin whose function is selected by the PORTECFG.2 bit.
PE2 is a bidirectional I/O port pin.
T2OUT is the active-HIGH output signal from 8051 Timer2. T2OUT
is active (HIGH) for one clock cycle when Timer/Counter 2 over-
flows.
Description