Philips HDD100 Service Manual page 11

PIN DESCRIPTIONS OF IC CY7C68013
Table 4-1. FX2 Pin Descriptions
128 100 56 56
TQFP TQFP SSOP QFN
71 56 38 31 CTL2 or
66 51
67 52
98 76
32 26 20 13 IFCLK
28 22
106 84
31 25
30 24
29 23
53 43
52 42
51 41
50 40
42
41 32
40 31
38
33 27 21 14 Reserved
101 79 51 44 WAKEUP
[5]
(continued)
Name Type Default
Output
FLAGC
CTL3 Output
CTL4 Output
CTL5 Output
I/O/Z
INT4 Input N/A
INT5# Input N/A
T2 Input N/A
T1 Input N/A
T0 Input N/A
RXD1 Input N/A
TXD1 Output
RXD0 Input N/A
TXD0 Output
CS# Output
WR# Output
RD# Output
OE# Output
Input N/A
Input N/A
3 - 6
H Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1..0].
CTL2 is a GPIF control output.
FLAGC is a programmable slave-FIFO output status flag signal.
Defaults to EMPTY for the FIFO selected by the FIFOADR[1:0]
pins.
H CTL3 is a GPIF control output.
H CTL4 is a GPIF control output.
H CTL5 is a GPIF control output.
Z Interface Clock, used for synchronously clocking data into or out of
the slave FIFOs. IFCLK also serves as a timing reference for all
slave FIFO control signals and GPIF. When internal clocking,
IFCONFIG.7 = 1, is used the IFCLK pin can be configured to output
30/48 MHz by bits IFCONFIG.5 and IFCONFIG.6. IFCLK may be
inverted, whether internally or externally sourced, by setting the bit
IFCONFIG.4 =1.
INT4 is the 8051 INT4 interrupt request input signal. The INT4 pin
is edge-sensitive, active HIGH.
INT5# is the 8051 INT5 interrupt request input signal. The INT5 pin
is edge-sensitive, active LOW.
T2 is the active-HIGH T2 input signal to 8051 Timer2, which pro-
vides the input to Timer2 when C/T2 = 1. When C/T2 = 0, Timer2
does not use this pin.
T1 is the active-HIGH T1 signal for 8051 Timer1, which provides
the input to Timer1 when C/T1 is 1. When C/T1 is 0, Timer1 does
not use this bit.
T0 is the active-HIGH T0 signal for 8051 Timer0, which provides
the input to Timer0 when C/T0 is 1. When C/T0 is 0, Timer0 does
not use this bit.
RXD1is an active-HIGH input signal for 8051 UART1, which pro-
vides data to the UART in all modes.
H TXD1is an active-HIGH output pin from 8051 UART1, which pro-
vides the output clock in sync mode, and the output data in async
mode.
RXD0 is the active-HIGH RXD0 input to 8051 UART0, which pro-
vides data to the UART in all modes.
H TXD0 is the active-HIGH TXD0 output from 8051 UART0, which
provides the output clock in sync mode, and the output data in
async mode.
H CS# is the active-LOW chip select for external memory.
H WR# is the active-LOW write strobe output for external memory.
H RD# is the active-LOW read strobe output for external memory.
H OE# is the active-LOW output enable for external memory.
Reserved. Connect to ground.
USB Wakeup. If the 8051 is in suspend, asserting this pin starts
up the oscillator and interrupts the 8051 to allow it to exit the sus-
pend mode. Holding WAKEUP asserted inhibits the EZ-USB chip
from suspending. This pin has programmable polarity (WAKE-
UP.4).
Description