Philips HDD100 Service Manual page 7

PIN DESCRIPTIONS OF IC CY7C68013
Table 4-1. FX2 Pin Descriptions
128 100 56 56
TQFP TQFP SSOP QFN
35
12 11 12 5
11 10 11 4
1 100 5 54 CLKOUT
Port A
82 67 40 33 PA0 or
83 68 41 34 PA1 or
84 69 42 35 PA2 or
85 70 43 36 PA3 or
89 71 44 37 PA4 or
90 72 45 38 PA5 or
91 73 46 39 PA6 or
[5]
(continued)
Name Type Default
EA Input N/A
XTALIN Input N/A
XTALOUT Output N/A
O/Z 12 MHz 12-, 24- or 48-MHz clock, phase locked to the 24-MHz input clock.
I/O/Z
INT0# (PA0)
I/O/Z
INT1# (PA1)
I/O/Z
SLOE (PA2)
I/O/Z
WU2 (PA3)
I/O/Z
FIFOADR0 (PA4)
I/O/Z
FIFOADR1 (PA5)
I/O/Z
PKTEND (PA6)
3 - 2
External Access. This pin determines where the 8051 fetches
code between addresses 0x0000 and 0x1FFF. If EA = 0 the 8051
fetches this code from its internal RAM. IF EA = 1 the 8051 fetches
this code from external memory.
Crystal Input. Connect this signal to a 24-MHz parallel-resonant,
fundamental mode crystal and 20-pF capacitor to GND.
It is also correct to drive XTALIN with an external 24 MHz square
wave derived from another clock source.
Crystal Output. Connect this signal to a 24-MHz parallel-resonant,
fundamental mode crystal and 20-pF capacitor to GND.
If an external clock is used to drive XTALIN, leave this pin open.
The 8051 defaults to 12-MHz operation. The 8051 may tri-state this
output by setting CPUCS.1 = 1.
I Multiplexed pin whose function is selected by:
PORTACFG.0
PA0 is a bidirectional IO port pin.
INT0# is the active-LOW 8051 INT0 interrupt input signal, which is
either edge triggered (IT0 = 1) or level triggered (IT0 = 0).
I Multiplexed pin whose function is selected by:
PORTACFG.1
PA1 is a bidirectional IO port pin.
INT1# is the active-LOW 8051 INT1 interrupt input signal, which is
either edge triggered (IT1 = 1) or level triggered (IT1 = 0).
I Multiplexed pin whose function is selected by two bits:
IFCONFIG[1:0].
PA2 is a bidirectional IO port pin.
SLOE is an input-only output enable with programmable polarity
(FIFOPOLAR.4) for the slave FIFOs connected to FD[7..0] or
FD[15..0].
I Multiplexed pin whose function is selected by:
WAKEUP.7 and OEA.3
PA3 is a bidirectional I/O port pin.
WU2 is an alternate source for USB Wakeup, enabled by WU2EN
bit (WAKEUP.1) and polarity set by WU2POL (WAKEUP.4). If the
8051 is in suspend and WU2EN = 1, a transition on this pin starts
up the oscillator and interrupts the 8051 to allow it to exit the sus-
pend mode. Asserting this pin inhibits the chip from suspending, if
WU2EN=1.
I Multiplexed pin whose function is selected by:
IFCONFIG[1..0].
PA4 is a bidirectional I/O port pin.
FIFOADR0 is an input-only address select for the slave FIFOs con-
nected to FD[7..0] or FD[15..0].
I Multiplexed pin whose function is selected by:
IFCONFIG[1..0].
PA5 is a bidirectional I/O port pin.
FIFOADR1 is an input-only address select for the slave FIFOs con-
nected to FD[7..0] or FD[15..0].
I Multiplexed pin whose function is selected by the IFCONFIG[1:0]
bits.
PA6 is a bidirectional I/O port pin.
PKTEND is an input-only packet end with programmable polarity
(FIFOPOLAR.5) for the slave FIFOs connected to FD[7..0] or
FD[15..0].
Description