Philips CEM3000B Service Manual page 53

1 Semiconductor
Read to Write Cycle (Same Bank) @CAS
0 1 2 3
CLK
CKE
CS
RAS
t
RCD
CAS
ADDR
Ra
A11
A10
Ra
DQ
WE
UDQM,
LDQM
Row Active
Read Command
*Note: 1. In Case CAS latency is 3, READ can be interrupted by WRITE.
The minimum command interval is [burst length + 1] cycles.
UDQM, LDQM must be high at least 3 clocks prior to the write command.
CAS Latency=2, Burst Length=4 CAS CAS
4 5 6 7 8
∗Note 1
Ca0 Cb0
Da0 Db0 Db1
Write Command
9 10 11 12 13 14
Db2 Db3
t
WR
Precharge Command
FEDD56V16160F-02
MSM56V16160F
15 16 17 18 19
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