Philips CEM3000B Service Manual page 52

1 Semiconductor
Clock Suspension & DQM Operation Cycle @CAS
0 1 2 3
CLK
CKE
CS
RAS
CAS
Ra Ca
ADDR
A11
Ra
A10
DQ
WE
UDQM,
LDQM
Row Active
Read Command
*Note: 1. When Clock Suspension is asserted, the next clock cycle is ignored.
2. When UDQM and LDQM are asserted, the read data after two clock cycles is masked.
3. When UDQM and LDQM are asserted, the write data in the same clock cycle is masked.
4. When LDQM is set High, the input/output data of DQ1 – DQ8 is masked.
5. When UDQM is set High, the input/output data of DQ9 – DQ16 is masked.
CAS CAS CAS Latency=2, Burst Length=4
4 5 6 7 8
∗Note 1
Qa0 Qa1 Qa2
t
OHZ
∗Note 2
CLOCK Read Command
Suspension
Read DQM
9 10 11 12 13 14
Cb
Qb0 Qb1
t
OHZ
Read DQM
Command
FEDD56V16160F-02
MSM56V16160F
15 16 17 18 19
∗Note 1
Cc
Dc0 Dc2
∗Note 3
Write Write DQM
DQM
Write CLOCK Suspension
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