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Aaeon EPIC-KBS7 User Manual

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EPIC-KBS7
EPIC Board
User's Manual 1
st
Ed
Last Updated: July 20, 2017

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  • Page 1 EPIC-KBS7 EPIC Board User’s Manual 1 Last Updated: July 20, 2017...
  • Page 2 AAEON assumes no liabilities resulting from errors or omissions in this document, or from the use of the information contained herein. AAEON reserves the right to make changes in the product design without notice to its users.
  • Page 3 Acknowledgement All other products’ name or trademarks are properties of their respective owners. Microsoft Windows is a registered trademark of Microsoft Corp.  Intel, Pentium, Celeron, and Xeon are registered trademarks of Intel Corporation  Core, Atom are trademarks of Intel Corporation ...
  • Page 4 Packing List Before setting up your product, please make sure the following items have been shipped: Item Quantity EPIC-KBS7  1702150155 SATA power cable  1709070500 SATA cable  9657666600 jumper cap  Product DVD with drivers  If any of these items are missing or damaged, please contact your distributor or sales representative immediately.
  • Page 5 (if any), its specifications, dimensions, jumper/connector settings/definitions, and driver installation instructions (if any), to facilitate users in setting up their product. Users may refer to the AAEON.com for the latest version of this document. Preface...
  • Page 6 Safety Precautions Please read the following safety instructions carefully. It is advised that you keep this manual for future references All cautions and warnings on the device should be noted. Make sure the power source matches the power rating of the device. Position the power cord so that people cannot step on it.
  • Page 7 If any of the following situations arises, please the contact our service personnel: Damaged power cord or plug Liquid intrusion to the device iii. Exposure to moisture Device is not working as expected or in a manner as described in this manual The device is dropped or damaged Any obvious signs of damage displayed on the device...
  • Page 8 FCC Statement This device complies with Part 15 FCC Rules. Operation is subject to the following two conditions: (1) this device may not cause harmful interference, and (2) this device must accept any interference received including interference that may cause undesired operation.
  • Page 9 China RoHS Requirements (CN) 产品中有毒有害物质或元素名称及含量 AAEON Main Board/ Daughter Board/ Backplane 有毒有害物质或元素 部件名称 铅 汞 镉 六价铬 多溴联苯 多溴二苯醚 (Pb) (Hg) (Cd) (Cr(VI)) (PBB) (PBDE) 印刷电路板 ○ ○ ○ ○ ○ ○ 及其电子组件 外部信号 ○ ○ ○ ○ ○ ○...
  • Page 10 China RoHS Requirement (EN) Poisonous or Hazardous Substances or Elements in Products AAEON Main Board/ Daughter Board/ Backplane Poisonous or Hazardous Substances or Elements Hexavalent Polybrominated Polybrominated Component Lead Mercury Cadmium Chromium Biphenyls Diphenyl Ethers (Pb) (Hg) (Cd) (Cr(VI)) (PBB) (PBDE) PCB &...

  • Page 11: Table Of Contents

    Table of Contents Chapter 1 - Product Specifications..................1 Specifications ......................2 Chapter 2 – Hardware Information ..................1 Dimensions ....................... 2 Jumpers and Connectors ..................5 List of Jumpers ......................7 2.3.1 LVDS Power select / LVDS BKLT Power select (JP4) ......8 2.3.2 LVDS BKLT control (JP5) ..............
  • Page 12 2.4.15 RS232 PIN Header (CN26) ............20 2.4.16 DIO PIN HEADER (CN24) .............. 21 CPU Installation ...................... 22 Chapter 3 - BIOS Setup ......................1 System Test and Initialization ................2 AMI BIOS Setup ....................... 3 Setup submenu: Main .................... 4 Setup submenu: Advanced ...................
  • Page 13 Appendix A - Watchdog Timer Programming ..............5 Watchdog Timer Initial Program ................6 Appendix B - I/O Information ....................11 I/O Address Map ....................12 Memory Address Map ..................14 IRQ Mapping Chart ....................16 Appendix B – Mating Connector Information ..............18 Mating Connector ....................

  • Page 14: Chapter 1 - Product Specifications

    Chapter 1 Chapter 1 - Product Specifications...

  • Page 15: Specifications

    Specifications System EPIC Board Form Factor  7th Gen. Intel ® Core™ i7/i5/i3/Celeron ® Processor  Xeon ® Up to 16 GB DDR4 (Non-ECC) 2133 MHz System Memory  Intel H110 (6W) ® Chipset  Fintek F81866D I/O Chipset  Intel 10/100/1000 Base LANs, RJ-45 x 2 Ethernet ...
  • Page 16 -40 ~ 80°C (-40 ~ 176°F) Storage Temperature  0 ~ 90%, relative humidity, non-condensing Operation Humidity  Display Processor-integrated Chipset  CRT/HDMI (Option: LVDS) Display Combination  LVDS 18/24bit, 2CH LCD Interface  2 x SATA SATA  USB3.0 x 4 (Real IO) ...

  • Page 17: Chapter 2 - Hardware Information

    Chapter 2 Chapter 2 – Hardware Information...

  • Page 18: Dimensions

    Dimensions Component Side Chapter 2 – Hardware Information...
  • Page 19 Chapter 2 – Hardware Information...
  • Page 20 Solder Side Chapter 2 – Hardware Information...

  • Page 21: Jumpers And Connectors

    Jumpers and Connectors Component Side Chapter 2 – Hardware Information...
  • Page 22 Solder Side Chapter 2 – Hardware Information...

  • Page 23: List Of Jumpers

    List of Jumpers Please refer to the table below for all of the board’s jumpers that you can configure for your application Label Function LVDS power Select CONN Backlight power select CONN Clean C-MOS PIN Header AT/ATX CONN Front Panel PIN Header Chapter 2 –...

  • Page 24: Lvds Power Select / Lvds Bklt Power Select (Jp4)

    2.3.1 LVDS Power select / LVDS BKLT Power select (JP4) LVDS Power select +3.3V (Default) LVDS BKLT Power select +12V +5V (Default) 2.3.2 LVDS BKLT control (JP5) +12V +5V (Default) Chapter 2 – Hardware Information...

  • Page 25: Rtc Reset Header (Jp6)

    2.3.3 RTC RESET header (JP6) Normal (Default) Clear CMOS 2.3.4 ATX/AT select (JP7) Disable Enable (Default) 2.3.5 Front Panel Header (JP9) Pin Name Pin Name EXT_PWRBTN# FP_HDLED- FP_HDLED+ FP_SPKR- +V5S PWRLED+ HWRST# Chapter 2 – Hardware Information...

  • Page 26: List Of Connectors

    List of Connectors Please refer to the table below for all of the board’s connectors that you can configure for your application Label Function Backlight CONN 2 PIN DC IN connector LVDS CONN 3 PIN SB Power IN connector AUDIO connector RTC Battery CONN SATA Power connector USB2.0 CONN...
  • Page 27 CN22 USB 3.0 Connector PC Buzzer CN23 HDMI CONN CN25 VGA CONN BOIS Socket CPU1 CPU Socket DIMM1 RAM Socket1 LED1 Stand By power LED indicate LED2 +V5S LED indicate LED3 HDD LED indicate Chapter 2 – Hardware Information...

  • Page 28: Backlight Conn (Cn1)

    2.4.1 Backlight CONN (CN1) Pin Name BLK_PWR BLK_CONTROL BKL_ENABLE 2.4.2 2 PIN DC IN connector (CN2) Pin Name +VIN 9~24V or 12V 2.4.3 LVDS CONN (CN3) Chapter 2 – Hardware Information...
  • Page 29 PIN 29 PIN 30 PIN 1 PIN 2 Pin Name BKL_ENABLE BKL_CONTROL LCD_PWR LVDS_A_CLK- LVDS_A_CLK+ LCD_PWR LVDS_DA0- LVDS_DA0+ LVDS_DA1- LVDS_DA1+ LVDS_DA2- LVDS_DA2+ LVDS_DA3- LVDS_DA3+ DDC_DATA DDC_CLK LVDS_DB0- Chapter 2 – Hardware Information...

  • Page 30: Pin Sb Power In Connector (Cn4)

    LVDS_DB0+ LVDS_DB1- LVDS_DB1+ LVDS_DB2- LVDS_DB2+ LVDS_DB3- LVDS_DB3+ LCD_PWR LVDS_B_CLK- LVDS_B_CLK+ 2.4.4 3 PIN SB Power IN connector (CN4) Pin Name PSON# +V5A_SB_IN Chapter 2 – Hardware Information...

  • Page 31: Audio Pin Header (Cn5)

    2.4.5 AUDIO PIN Header (CN5) Pin Name MIC_L MIC_R LIN_L LIN_R LOUT_L LOUT_R +VDD_AUD 2.4.6 RTC Battery CONN (CN6) Pin Name Chapter 2 – Hardware Information...

  • Page 32: Sata Power Connector (Cn7)

    RTCVCC 2.4.7 SATA Power connector (CN7) Pin Name 2.4.8 USB PIN Header (CN8 / CN9) Pin Name USBD- USBD+ Chapter 2 – Hardware Information...

  • Page 33: Sata Port 1/Sata Port 2 (Cn10/Cn13)

    2.4.9 SATA Port 1/SATA Port 2 (CN10/CN13) Pin Name Pin Name SATA_TXP0 SATA_TXP1 SATA_TXN0 SATA_TXN1 SATA_RXN0 SATA_RXN1 SATA_RXP0 SATA_RXP1 2.4.10 External FAN PIN Header (CN14) Pin Name +VCC_FAN_CPU_CON FAN_TAC_CPU_CON FAN_CTL_CPU_CON Chapter 2 – Hardware Information...

  • Page 34: Lpc Connector For Debug (Cn15)

    2.4.11 LPC connector for debug (CN15) Pin Name LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3 P3V3 FRAME# RST# LDRQ0 LDRQ1 INT_SERIRQ 2.4.12 RS232/422/485 PIN Header (CN16) Chapter 2 – Hardware Information...

  • Page 35: Rs232 Pin Header (Cn17)

    Pin Name DCD2 DSR2 RTS2 CTS2 DTR2 2.4.13 RS232 PIN Header (CN17) Pin Name DCD1 Chapter 2 – Hardware Information...

  • Page 36: Rs232 Pin Header (Cn18)

    DSR1 RTS1 CTS1 DTR1 2.4.14 RS232 PIN Header (CN18) Pin Name DCD3 DSR3 RTS3 CTS3 DTR3 2.4.15 RS232 PIN Header (CN26) Chapter 2 – Hardware Information...

  • Page 37: Dio Pin Header (Cn24)

    Pin Name DCD4 DSR4 RTS4 CTS4 DTR4 2.4.16 DIO PIN HEADER (CN24) DIO0 DIO1 DIO2 DIO3 DIO4 DIO5 DIO6 DIO7 Pin Name Pin Name Chapter 2 – Hardware Information...

  • Page 38: Cpu Installation

    +V5S CPU Installation Turn off the system, unplug the power cord and make sure the system is off.  Have Intel Kabylake or Intel SkyLake-S FCLGA1151 Processor (Max. TDP 35W)  ready. Step 1: Remove the plastic cover as instructed below. Step 2: Assemble the CPU.
  • Page 39 Step3: Assemble the cover, and make sure that the corners align. Step 4: Push the cover down so that it fits. Chapter 2 – Hardware Information...
  • Page 40 Step 7: Install the sponge. Chapter 2 – Hardware Information...

  • Page 41: Chapter 3 - Bios Setup

    Chapter 3 Chapter 3 - BIOS Setup...

  • Page 42: System Test And Initialization

    System Test and Initialization These routines test and initialize board hardware. If the routines encounter an error during the tests, you will either hear a few short beeps or see an error message on the screen. There are two kinds of errors: fatal and non-fatal. The system can usually continue the boot up sequence with non-fatal errors.

  • Page 43: Ami Bios Setup

    AMI BIOS Setup AMI BIOS ROM has a built-in Setup program that allows users to modify the basic system configuration. This type of information is stored in battery-backed CMOS RAM and BIOS NVRAM so that it retains the Setup information when the power is turned off. Entering Setup Power on the computer and press <Del>or <ESC>...

  • Page 44: Setup Submenu: Main

    Setup submenu: Main Chapter 3 – BIOS Setup...

  • Page 45: Setup Submenu: Advanced

    Setup submenu: Advanced Chapter 3 – BIOS Setup...

  • Page 46: Cpu Configuration

    3.4.1 CPU Configuration Options summary: Intel (VMX) Disabled Virtualization Enabled Optimal Default, Failsafe Technology Default When enabled, a VMM can utilize the additional hardware capabilities provided by Vanderpool Technology. C states Disabled Enabled Optimal Default, Failsafe Default Enabled for Windows XP and Linux (OS optimized for Hyper-Threading Technology) and Disable for other OS (OS not optimized for Hyper-Threading Technology).

  • Page 47: Sata Configuration

    3.4.2 SATA Configuration Options summary: SATA Enabled Optimal Default, Failsafe Controller(s) Default Disabled Enable or disable SATA Device. SATA Mode AHCI Mode Optimal Default, Failsafe Default RAID Mode Determines how SATA controller(s) operate. Port 0 Disabled Enabled Optimal Default, Failsafe Default Enable or Disable SATA Port.
  • Page 48 Enabled Designates this port as Hot Pluggable. Chapter 3 – BIOS Setup...

  • Page 49: Sio Configuration

    3.4.3 SIO Configuration Chapter 3 – BIOS Setup...

  • Page 50: Serial Port Configuration

    3.4.3.1 Serial Port Configuration Options summary: Use This Disabled Optimal Default, Failsafe Default Device Enabled En/Disable Serial Port (COM) Optimal Default, Failsafe Default Possible: Use Automatic Settings IO=2F8; IRQ=3; IO=3F8; IRQ=4; Select an optimal setting for IO device Optimal Default, Failsafe Default mode RS232 RS422...

  • Page 51: Hardware Monitor

    3.4.4 Hardware Monitor Options summary: Fan1 Smart Manual RPM Mode Fan control Manual Duty Mode Auto RPM Mode Optimal Default, Failsafe Auto Duty-Cycle Default Mode Chapter 3 – BIOS Setup...

  • Page 52: Cpu Smart Fan Mode Configuration

    3.4.4.1 CPU Smart Fan Mode Configuration Options summary: Manual Setting 3000 Optimal Default, Failsafe Default Set Fan at fixed RPM Chapter 3 – BIOS Setup...
  • Page 53 Options summary: Manual Setting 60 Optimal Default, Failsafe Default Set Fan at fixed Duty-Cycle Min=0 Max=100 Please input Dec number: Chapter 3 – BIOS Setup...
  • Page 54 Chapter 3 – BIOS Setup...

  • Page 55: Usb Configuration

    3.4.5 USB Configuration Options summary: Legacy USB Support Enabled Optimal Default, Failsafe Default Disabled Auto Enables BIOS Support for Legacy USB Support. When enabled, USB can be functional in legacy environment like DOS. AUTO option disables legacy support if no USB devices are connected Device Name Auto...

  • Page 56: Digital Io Port Configuration

    If Auto. USB devices less than 530MB will be emulated as Floppy and remaining as Floppy and remaining as hard drive. Forced FDD option can be used to force a HDD formatted drive to boot as FDD(Ex. ZIP drive) USB Port 0/1 function FCH USB port Optimal Default, Failsafe routing...
  • Page 57 Chapter 3 – BIOS Setup...

  • Page 58: Power Management

    3.4.7 Power Management Options summary: Power Mode ATX Type Optimal Default, Failsafe Default AT Type Select power supply mode. Restore on Last State Optimal Default, Failsafe Power Loss Default Power On Power Off Select power state when power is re-applied after a power failure. RTC wake Disabled Optimal Default, Failsafe...
  • Page 59 Enable or disable System wake on alarm event. When enabled, System will wake on the hr::min::sec specified Chapter 3 – BIOS Setup...

  • Page 60: Submenu Chipset

    Submenu Chipset Chapter 3 – BIOS Setup...

  • Page 61: System Agent (Sa) Configuration

    3.5.1 System Agent (SA) Configuration Options summary: Max TOLUD Dynamic Optimal Default, Failsafe Default 1 GB 1.25 GB 1.5 GB 1.75 GB 2 GB 2.25 GB 2.5 GB 2.75 GB 3 GB 3.25 GB Maximum Value of TOLUD Dynamic assignment would adjust TOLUD automatically based on largest MMIO length of installed graphic controller.
  • Page 62 PEG Port Gen Auto Optimal Default, Failsafe Speed Default Gen1 Gen2 Gen3 Configure PED 0:1:0 Max Speed Chapter 3 – BIOS Setup...

  • Page 63: Graphics Configuration

    3.5.1.1 Graphics Configuration Options summary: Primary Display Auto Optimal Default, Failsafe Default IGFX PCIE Select which of IGFX/PEG Graphics dvice should be Primary Display. Primary IGFX Boot VBIOS Default Optimal Default, Failsafe Display Default LVDS HDMI Chapter 3 – BIOS Setup...
  • Page 64 Select the Video Device which will be activated during POST. This has no effect if external graphic present. Secondary boot display selection will appear based on your selection. Secondary IGFX Disabled Optimal Default, Failsafe Boot Display Default HDMI Select Secondary Display Device Chapter 3 –...

  • Page 65: Lvds Panel Configuration

    3.5.1.2 LVDS Panel Configuration Options summary: LVDS Disabled Enabled Optimal Default, Failsafe Default Enable/Disabled this panel. LVDS Panel Type 640x480@60Hz 800x480@60Hz 800x600@60Hz 1024x600@60Hz 1024x768@60Hz Optimal Default, Failsafe Default 1280x768@60Hz 1280x800@60Hz 1280x1024@60Hz 1366x768@60Hz Chapter 3 – BIOS Setup...
  • Page 66 1440x900@60Hz 1600x1200@60Hz 1920x1080@60Hz 1920x1200@60Hz Select LCD panel used by Internal Graphics Device by selecting the appropriate setup item. Color Depth 18-bit Optimal Default, Failsafe Default 24-bit 36-bit 48-bit Select panel type Backlight Type Normal Optimal Default, Failsafe Default Inverted Select backlight control signal type Backlight Level Optimal Default, Failsafe Default...
  • Page 67 500Hz 1KHz 2.2KHz 6.5KHz Select PWM frequency of backlight control signal Chapter 3 – BIOS Setup...

  • Page 68: Pch-Io Configuration

    3.5.2 PCH-IO Configuration Options summary: Full-MiniCard Slot SATA Optimal Default, Failsafe Function Default PCIe Switch minicard slot function (Excluding H110 SKU) PCI Express Root Port 15 Disabled Enabled Optimal Default, Failsafe Default Control the PCIE root port PCIe Speed Auto Optimal Default, Failsafe Default Gen1...
  • Page 69 Chapter 3 – BIOS Setup...

  • Page 70: Security

    Security Change User/Supervisor Password You can install a Supervisor password, and if you install a supervisor password, you can then install a user password. A user password does not provide access to many of the features in the Setup utility. If you highlight these items and press Enter, a dialog box appears which lets you enter a password.
  • Page 71 Highlight this item and type in the current password. At the next dialog box press Enter to disable password protection. Chapter 3 – BIOS Setup...

  • Page 72: Submenu: Boot

    Submenu: Boot Options summary: Quiet Boot Disabled Enabled Optimal Default, Failsafe Default En/Disable showing boot logo. Launch PXE OpROM Disabled Optimal Default, Failsafe Default Enabled Controls the execution of UEFI and Legacy PXE OpROm Chapter 3 – BIOS Setup...

  • Page 73: Bbs Priorities

    3.7.1 BBS Priorities Chapter 3 – BIOS Setup...

  • Page 74: Submenu: Exit

    Submenu: Exit Chapter 3 – BIOS Setup...

  • Page 75: Chapter 4 - Drivers Installation

    Chapter 4 Chapter 4 – Drivers Installation...

  • Page 76: Product Cd/Dvd

    Product CD/DVD The EPIC-KBS7 comes with a product DVD that contains all the drivers and utilities you need to setup your product. Insert the DVD and follow the steps in the autorun program to install the drivers. In case the program does not start, follow the sequence below to install the drivers.
  • Page 77 Open the .exe file in the folder Follow the instructions Drivers will be installed automatically Step 4 – Install Audio Driver Open the STEP4 – Audio folder and select your OS Open the Setup.exe file in the folder Follow the instructions Drivers will be installed automatically Step 5 –...
  • Page 78 Drivers will be installed automatically Step 9 – Install USB 3.0 Driver Open the STEP9 – USB 3.0 folder and select your OS Open the Setup.exe file in the folder Follow the instructions Drivers will be installed automatically Chapter 4 – Driver Installation...

  • Page 79: Appendix A - Watchdog Timer Programming

    Appendix A Appendix A - Watchdog Timer Programming...

  • Page 80: Watchdog Timer Initial Program

    Watchdog Timer Initial Program Table 1 : Super I/O relative register table Default Value Note SIO MB PnP Mode Index Register Index 0x2E(Note1) 0x2E or 0x4E SIO MB PnP Mode Data Register Data 0x2F(Note2) 0x2F or 0x4F Table 2 : Watchdog relative register table Register BitNum Value...
  • Page 81 ************************************************************************************ // SuperIO relative definition (Please reference to Table 1) #define byte SIOIndex //This parameter is represented from Note1 #define byte SIOData //This parameter is represented from Note2 #define void IOWriteByte(byte IOPort, byte Value); #define byte IOReadByte(byte IOPort); // Watch Dog relative definition (Please reference to Table 2) #define byte TimerLDN //This parameter is represented from Note3 #define byte TimerReg //This parameter is represented from Note4 #define byte TimerVal // This parameter is represented from Note24...
  • Page 82 ************************************************************************************ VOID Main(){ // Procedure : AaeonWDTConfig // (byte)Timer : Time of WDT timer.(0x00~0xFF) // (boolean)Unit : Select time unit(0: second, 1: minute). AaeonWDTConfig(); // Procedure : AaeonWDTEnable // This procudure will enable the WDT counting. AaeonWDTEnable(); ************************************************************************************ Appendix A – Watchdog Timer Programming...
  • Page 83 ************************************************************************************ // Procedure : AaeonWDTEnable VOID AaeonWDTEnable (){ WDTEnableDisable(EnableLDN, EnableReg, EnableBit, 1); // Procedure : AaeonWDTConfig VOID AaeonWDTConfig (){ // Disable WDT counting WDTEnableDisable(EnableLDN, EnableReg, EnableBit, 0); // Clear Watchdog Timeout Status WDTClearTimeoutStatus(); // WDT relative parameter setting WDTParameterSetting(); VOID WDTEnableDisable(byte LDN, byte Register, byte BitNum, byte Value){ SIOBitSet(LDN, Register, BitNum, Value);...
  • Page 84 ************************************************************************************ VOID SIOEnterMBPnPMode(){ IOWriteByte(SIOIndex, 0x87); IOWriteByte(SIOIndex, 0x87); VOID SIOExitMBPnPMode(){ IOWriteByte(SIOIndex, 0xAA); VOID SIOSelectLDN(byte LDN){ IOWriteByte(SIOIndex, 0x07); // SIO LDN Register Offset = 0x07 IOWriteByte(SIOData, LDN); VOID SIOBitSet(byte LDN, byte Register, byte BitNum, byte Value){ Byte TmpValue; SIOEnterMBPnPMode(); SIOSelectLDN(byte LDN); IOWriteByte(SIOIndex, Register); TmpValue = IOReadByte(SIOData);...

  • Page 85: Appendix B - I/O Information

    Appendix B Appendix B - I/O Information...

  • Page 86: I/O Address Map

    I/O Address Map Appendix B – I/O Information...
  • Page 87 Appendix B – I/O Information...

  • Page 88: Memory Address Map

    Memory Address Map Appendix B – I/O Information...
  • Page 89 Appendix B – I/O Information...

  • Page 90: Irq Mapping Chart

    IRQ Mapping Chart Appendix B – I/O Information...
  • Page 91 Appendix B – I/O Information...

  • Page 92: Appendix B - Mating Connector Information

    Appendix C Appendix B – Mating Connector Information...

  • Page 93: Mating Connector

    Mating Connector Mating Connector Connector Available Function Cable P/N Label Vendor Model no Cable LVDS Invertor PHR-5 Connector +9~24V Vin Power 1702002010 Connector Cable LVDS DF13-30DS HIROSE Connector -1.25C External +5VSB Power Input PHR-3 ATX Cable 170220020B PS_ON# Audio Audio Molex 51021-1000 1709100254...
  • Page 94 Cable Digital I/O CN24 Neltron 2026B-10 Connector Serial COM Port 4 CN26 Molex 51021-0900 Port 1701090150 Connector Cable...

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