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2. Before Starting
The main components of the CASTLE board shown in Figures 2.7 and 2.8 are described below.
Connectors
1)
Host interface connector CON1 (Master)
This is connected to J4 on the Cinderella board and is used when writing ROM data to the
flash memory on the Cinderella board.
The CON1 pin layout is shown in Table 2.7.
connector
CON1
12
Table 2.7 CASTLE CON1
No.
I/O
CASTLE CON1
1
-
VDD1 (+5 V)
2
-
VDD2 (+3.3 V)
3
-
VDD3 (+1.8 V)
4
-
CLOCK_OUT
5
-
NRESET
6
O
SCKM
7
O
SOM
8
I
SIM
9
O
NSCSM
10
-
MSGRDY
11
-
STBYEXIT
12
-
MUTE
13
P
VSS
14
P
VSS
15
P
VSS
16
P
VSS
EPSON
Cinderella J11
signal level
-
-
-
-
-
-
-
-
-
-
SCKS_FLASH
3.3 V LVCMOS
SIS_FLASH
3.3 V LVCMOS
SOS_FLASH
3.3 V LVCMOS
NSCSM_FLASH
3.3 V LVCMOS
-
-
-
-
-
-
VSS
-
VSS
-
VSS
-
VSS
-
S1V30080 Series Evaluation Board User's Guide
(Rev. 1.00)
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