A110 Universal Parallel/Serial Interface Module (Option 02) - Tektronix MTX100B Service Manual

HOTLink transmitter and
Cable Drivers
Cable Equalizer and
HOTLink Receiver
2.5 V Regulator

A110 Universal Parallel/Serial Interface Module (Option 02)

Local Bus Interface
FPGA
MTX100B MPEG Recorder and Player
Packet Mode Operation. The FIFO shift register is used to output the data on a
packet-by-packet basis. This FIFO has 9 bits of width and a depth of 512 stages.
The content of 9-bit width is 8 bits for data and 1 bit for Sync Bit. The Sync bit
indicates the location of sync pattern (47h) in the data.
The data sent from the A12 board is fed to the FIFO. The FIFO output port
searches for a Sync Bit. When a Sync Bit is detected, data output from the FIFO
is stopped, and the data that follows the Sync Bit is stored in the FIFO.
The FIFO input port also searches for a Sync Bit. When the port detects a Sync
Bit in the next packet, it sends the detection to the read-out controller at the FIFO
output port. When the FIFO output port receives the Sync Bit detection signal
from the input port, the output port reads out the signals until the next packet Sync
Bit is detected. The data rate of FIFO input port is equal to the data transfer rate of
the MTX100B, and that of output port is 216 Mbps (with the clock of 27 MHz),
which is used for the ASI output.
The HOTLink transmitter converts parallel signals from the FIFO to a serial signal.
The converted signal is output to the BNC connectors through the cable drivers.
The signal applied to the BNC connector is equalized by the cable equalizer, and is
converted to parallel signals by the HOTLink receiver. In addition, the equalized
signal is applied to the cable driver, and is output to the ASI through output.
The regulator supplies power for the internal circuitry in the FPGA.
The A110 Universal Parallel/Serial Interface module consists of the following
blocks:
The local bus interface communicates with the A12 Main board. There are two
sets of 16-bit signal lines for Rx and Tx: 8-bit data lines for single-end connection,
4-bit control lines for single-end connection, and 4-bit control lines for differential
connection. These lines are connected to the A12 Main board individually.
The FPGA consists of an 8-bit-to-1-bit shift register for parallel to serial
conversion, a 1-bit-to-8-bit shift register for serial to parallel conversion, and a PCI
interface. The shift registers are not used in the parallel data input/output mode.
There is a 32-bit resistor in the PCI interface. It controls the board operation.
Theory of Operation
2–5