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This user guide describes the characteristics, operation, and use of the THS3215EVM and THS317EVM
(THS321xEVM). This evaluation module (EVM) is a demonstration fixture for the
family of wideband, differential DAC to single-ended line drivers. The EVM provides 50-Ω input and output
termination for easy evaluation with common 50-Ω test equipment. A complete circuit description,
schematic diagram, printed circuit board (PCB) layout, and bill of materials are included.
Throughout this document, the terms demonstration kit, evaluation board, evaluation module, and EVM
are synonymous with the THS321xEVM.
All trademarks are the property of their respective owners.
SBOU161A – February 2016 – Revised April 2016
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THS3215EVM and THS3217EVM
Copyright © 2016, Texas Instruments Incorporated
SBOU161A – February 2016 – Revised April 2016
THS3215 andTHS3217
THS3215EVM and THS3217EVM
User's Guide
1
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Summary of Contents for Texas Instruments THS3215EVM
- Page 1 User's Guide SBOU161A – February 2016 – Revised April 2016 THS3215EVM and THS3217EVM This user guide describes the characteristics, operation, and use of the THS3215EVM and THS317EVM (THS321xEVM). This evaluation module (EVM) is a demonstration fixture for the THS3215 andTHS3217 family of wideband, differential DAC to single-ended line drivers.
- Page 2 Layer 5: GND Plane ..................... Layer 6: Bottom Signal Layer List of Tables ....................Bidirectional Switch Settings ..................Bill of Materials, THS321x EVM THS3215EVM and THS3217EVM SBOU161A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
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Page 3: Introduction
Interface to the OPS output pin, VOUT, through J7 (TP10). • Interface to the OPS inverting input pin, VIN–, through J6. SBOU161A – February 2016 – Revised April 2016 THS3215EVM and THS3217EVM Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated... -
Page 4: Design Considerations
CS_SW (PATHSEL control) OPS external, noninverting path Internal path from D2S to OPS PD_SW (DISABLE control) OPS off OPS on THS3215EVM and THS3217EVM SBOU161A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated... -
Page 5: Midscale Buffer Configuration Options
10.0k Junc Vocm 10.0 1.00 56.2 49.9 PATHSEL DISABLE 0.22µF -VCC2 -VCC1 -Vcc2 -Vcc1 Figure 3. Midscale Buffer Configuration Options SBOU161A – February 2016 – Revised April 2016 THS3215EVM and THS3217EVM Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated... -
Page 6: D2S Input Connection Options
Uninstall all the RLC filter components if not used in the application to prevent loading the D2S output Figure 4. D2S Input Connection Options THS3215EVM and THS3217EVM SBOU161A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated... -
Page 7: Mhz Butterworth Filter Before D2S Inputs
THS321x (see Figure 4). The output of the filter then drives the external noninverting input of the OPS, VIN+ (pin 9). SBOU161A – February 2016 – Revised April 2016 THS3215EVM and THS3217EVM Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated... -
Page 8: Ops Input And Output Connection Options
This section provides a complete schematic diagram, PCB layout, and bill of materials (BOM) for the THS321xEVM. Schematic Figure 7 shows the schematic. THS3215EVM and THS3217EVM SBOU161A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated... -
Page 9: Evm Schematic
Schematic, PCB Layout, and Bill of Materials www.ti.com Figure 7. EVM Schematic SBOU161A – February 2016 – Revised April 2016 THS3215EVM and THS3217EVM Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated... -
Page 10: Layer 1: Top Signal Layer
The PCB layers are shown in Figure 8 through Figure Figure 8. Layer 1: Top Signal Layer Figure 9. Layer 2: GND Plane THS3215EVM and THS3217EVM SBOU161A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated... -
Page 11: Layer 3: Power Plane, ±V
Schematic, PCB Layout, and Bill of Materials www.ti.com Figure 10. Layer 3: Power Plane, ±V Figure 11. Layer 4: Power Plane, ±V SBOU161A – February 2016 – Revised April 2016 THS3215EVM and THS3217EVM Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated... -
Page 12: Layer 5: Gnd Plane
Schematic, PCB Layout, and Bill of Materials www.ti.com Figure 12. Layer 5: GND Plane Figure 13. Layer 6: Bottom Signal Layer THS3215EVM and THS3217EVM SBOU161A – February 2016 – Revised April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated... -
Page 13: Bill Of Materials, Ths321X Evm
Bill of Materials Table 2 lists the bill of materials for the THS321xEVM. The BOMs for the THS3215EVM and THS3217EVM are identical except for the line item corresponding to the DUT model populated on the EVM. Table 2. Bill of Materials, THS321x EVM... -
Page 14: Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Original (February 2016) to A Revision ....................Page ..............• Added THS3215EVM and related information to this user's guide ......................• Changed front page EVM photo ................•... -
Page 15: Important Notice
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue.
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