Kenwood TK-80 Service Manual page 12

2-3. LO2 (PLL loop)
The part oscillated by X502 and Q517 is output to LO1
cancel loop after passing through the Q518 buffer and input
into mixer IC505. The other part is output from CN502 as
LO2.
2-4. CAR
A digital signal is generated near 695kHz at IC501, and the
analog signal converted by the CP502, CP503 ladder resis-
tors and Q522 D/A converter are mixed with the 10MHz gen-
erated from the chop output of IC501 at IC506. This is then
output as 10.695MHz through the band-pass filter and the
amplifier.
During receiving AM mode, the DDS oscillation is
stopped. In FSK mode, the internal register of IC501 is
switched for direct FSK modulation by the external RTK sig-
nal during selective call mode code transmission by the ABSL
signal from the CPU.
2-5. DDS circuit configuration
The DDS IC has been developed with standard cells to
implement a high-speed circuit and large-capacity ROM at
low cost.
OPTION
SO-2
Q525
2SC2714(Y) 2SC2714(Y)
OSC
20MHz
2SC2712(Y)
IC500
F71022Z
DDS1
1.195~
1.695MHz
CHOP
10MHz
DDS2
IC501
F71022Z
695kHz+∆
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CIRCUIT DESCRIPTION
IC502
Q526 Q527
MB86001PF
2SC2996(Y)
Rin
1/40
15
Q529 Q528
N=39~99
2SC2996(Y)
PLL
Q514
IC504
2SC2712(GR)
NJM2594V
–
LPF
+
8.805MHz
Q516
2SC2712(Y)
2SC2714(Y)
LPF OSC
Q523
2SC2712(Y)
+
+
LPF
Q522 IC506
2SC2712(GR) NJM2594V
Fig. 2 PLL block diagram and frequency configuration
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■ IC configuration
IC configuration is as follows:
• There are two 28 bit registers for setting frequency data,
one 28 bit frequency shift register for addition to the fre-
quency registers, a 23 bit parallel signal input section for
frequency modulation with parallel signals, and a data en-
try and selection section.
• There is a frequency-modulation section comprising 28 bit
adders for adding frequency data and frequency modula-
tion data, a phase data operation section that adds data
from the frequency modulation section and 28 bit phase
data register, and a SIN-ROM that converts phase data to
sine waves.
■ Frequency/shift data setting
Using serial signals synchronized with clock pulses, 30
bits (2 bits that specify the destination for which data is set,
and 28 bits of frequency data) are set in the three internal
registers.
■ Frequency register selection
The data set in the two frequency registers is selected by
the SLAB input of the DDS IC. This pin handles the ABSL
signal for IC501, and the CASL signal for IC500. This function
eliminates the need for the TK-80 to set frequency data for
each transmission/reception with the microprocessor.
Q531,533,535
2SK508NV(K52)
VCO1
Q508~510
2SC3722K(R)
DO2 VCO2
PD A. LPF
9
VCO3
Q512
1/N
2SC2712(Y)
Fin
BPF
6
Q511 19.5~
2SC2714(Y) 49.5MHz
IC505
UPC1686G
–
BPF BPF
+
8.305~ Q515 53.545~
2SC2712(Y) 54.045MHz
Q517
Q519
2SC2714(Y)
62.35MHz
Q518
2SC2714(Y)
CF500
10.695MHz
VCO1: 73.145~83.544MHz
VCO2: 83.545~94.544MHz
VCO3: 94.545~103.045MHz
Q536
2SC2714(Y)
LPF
Q507
2SC2714(Y)
IC503
NJM2594V
+
–
Q513
2SC2714(Y)
Q520
2SC2714(Y)
Q521
2SC2714(Y)
Q524
2SC2714(Y)
TK-80
LO1
: 73.145~
103.045MHz
3.4dBm
LO2
: 62.35MHz
2.5dBm
CAR
: 10.695MHz
–1.2dBm
11